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/linux-5.10/Documentation/devicetree/bindings/mmc/
Dsynopsys-dw-mshc-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: "mmc-controller.yaml#"
13 - Ulf Hansson <ulf.hansson@linaro.org>
20 reset-names:
23 clock-frequency:
29 fifo-depth:
31 The maximum size of the tx/rx fifo's. If this property is not
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Dzx-dw-mshc.txt7 by synopsys-dw-mshc.txt and the properties used by the ZTE specific
13 - "zte,zx296718-dw-mshc": for ZX SoCs
18 compatible = "zte,zx296718-dw-mshc";
21 fifo-depth = <32>;
22 data-addr = <0x200>;
23 fifo-watermark-aligned;
24 bus-width = <4>;
25 clock-frequency = <50000000>;
27 clock-names = "biu", "ciu";
28 max-frequency = <50000000>;
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Dsynopsys-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: "synopsys-dw-mshc-common.yaml#"
13 - Ulf Hansson <ulf.hansson@linaro.org>
18 const: snps,dw-mshc
33 clock-names:
35 - const: biu
36 - const: ciu
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/linux-5.10/drivers/iio/imu/inv_icm42600/
Dinv_icm42600_buffer.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 * struct inv_icm42600_fifo - FIFO state variables
20 * @on: reference counter for FIFO on.
21 * @en: bits field of INV_ICM42600_SENSOR_* for FIFO EN bits.
22 * @period: FIFO internal period.
23 * @watermark: watermark configuration values for accel and gyro.
24 * @count: number of bytes in the FIFO data buffer.
25 * @nb: gyro, accel and total samples in the FIFO data buffer.
26 * @data: FIFO data buffer aligned for DMA (2kB + 32 bytes of read cache).
35 } watermark; member
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Dinv_icm42600.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
67 /* ODR suffixed by LN or LP are Low-Noise or Low-Power mode only */
86 /* Low-Noise mode sensor data filter (3rd order filter by default) */
89 /* Low-Power mode sensor data filter (averaging) */
100 #define INV_ICM42600_SENSOR_CONF_INIT {-1, -1, -1, -1}
115 * struct inv_icm42600_state - driver state variables
127 * @buffer: data transfer buffer aligned for DMA.
128 * @fifo: FIFO management structure.
144 struct inv_icm42600_fifo fifo; member
188 /* all sensor data are 16 bits (2 registers wide) in big-endian */
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Dinv_icm42600_accel.c1 // SPDX-License-Identifier: GPL-2.0-or-later
74 * IIO buffer data: size must be a power of 2 and timestamp aligned
91 /* 3-axis accel + temperature */
96 /* enable accelerometer sensor and FIFO write */
109 mutex_lock(&st->lock); in inv_icm42600_accel_update_scan_mode()
128 /* update data FIFO write */ in inv_icm42600_accel_update_scan_mode()
130 ret = inv_icm42600_buffer_set_fifo_en(st, fifo_en | st->fifo.en); in inv_icm42600_accel_update_scan_mode()
137 mutex_unlock(&st->lock); in inv_icm42600_accel_update_scan_mode()
152 struct device *dev = regmap_get_device(st->map); in inv_icm42600_accel_read_sensor()
158 if (chan->type != IIO_ACCEL) in inv_icm42600_accel_read_sensor()
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Dinv_icm42600_gyro.c1 // SPDX-License-Identifier: GPL-2.0-or-later
74 * IIO buffer data: size must be a power of 2 and timestamp aligned
91 /* 3-axis gyro + temperature */
96 /* enable gyroscope sensor and FIFO write */
109 mutex_lock(&st->lock); in inv_icm42600_gyro_update_scan_mode()
128 /* update data FIFO write */ in inv_icm42600_gyro_update_scan_mode()
130 ret = inv_icm42600_buffer_set_fifo_en(st, fifo_en | st->fifo.en); in inv_icm42600_gyro_update_scan_mode()
137 mutex_unlock(&st->lock); in inv_icm42600_gyro_update_scan_mode()
152 struct device *dev = regmap_get_device(st->map); in inv_icm42600_gyro_read_sensor()
158 if (chan->type != IIO_ANGL_VEL) in inv_icm42600_gyro_read_sensor()
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/linux-5.10/drivers/net/wireless/intel/iwlwifi/fw/api/
Dsf.h8 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
31 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
32 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
66 /* Smart Fifo state */
75 /* Smart Fifo possible scenario */
88 /* smart FIFO default values */
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/linux-5.10/drivers/iio/imu/st_lsm6dsx/
Dst_lsm6dsx_buffer.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * STMicroelectronics st_lsm6dsx FIFO buffer library driver
5 * LSM6DS3/LSM6DS3H/LSM6DSL/LSM6DSM/ISM330DLC/LSM6DS3TR-C:
6 * The FIFO buffer can be configured to store data from gyroscope and
8 * specific pattern based on 'FIFO data sets' (6 bytes each):
9 * - 1st data set is reserved for gyroscope data
10 * - 2nd data set is reserved for accelerometer data
11 * The FIFO pattern changes depending on the ODRs and decimation factors
12 * assigned to the FIFO data sets. The first sequence of data stored in FIFO
13 * buffer contains the data of all the enabled FIFO data sets
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/linux-5.10/arch/powerpc/platforms/512x/
Dmpc512x_lpbfifo.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * The driver for Freescale MPC512x LocalPlus Bus FIFO
6 * Copyright (C) 2013-2015 Alexander Popov <alex.popov@linux.com>.
21 #include <linux/dma-direction.h>
22 #include <linux/dma-mapping.h>
61 * mpc512x_lpbfifo_irq - IRQ handler for LPB FIFO
76 if (!req || req->dir == MPC512X_LPBFIFO_REQ_DIR_READ) { in mpc512x_lpbfifo_irq()
81 status = in_be32(&lpbfifo.regs->status); in mpc512x_lpbfifo_irq()
84 out_be32(&lpbfifo.regs->enable, in mpc512x_lpbfifo_irq()
89 out_be32(&lpbfifo.regs->status, MPC512X_SCLPC_SUCCESS); in mpc512x_lpbfifo_irq()
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/linux-5.10/drivers/gpu/drm/mcde/
Dmcde_display.c1 // SPDX-License-Identifier: GPL-2.0
5 * (C) ST-Ericsson SA 2013
9 #include <linux/dma-buf.h>
28 /* TODO: implement FIFO C0 and FIFO C1 */
72 mispp = readl(mcde->regs + MCDE_MISPP); in mcde_display_irq()
73 misovl = readl(mcde->regs + MCDE_MISOVL); in mcde_display_irq()
74 mischnl = readl(mcde->regs + MCDE_MISCHNL); in mcde_display_irq()
84 if (mcde_dsi_irq(mcde->mdsi)) { in mcde_display_irq()
93 if (mcde->flow_mode == MCDE_COMMAND_ONESHOT_FLOW) { in mcde_display_irq()
94 spin_lock(&mcde->flow_lock); in mcde_display_irq()
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/linux-5.10/arch/arm64/boot/dts/zte/
Dzx296718.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/input/input.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/gpio/gpio.h>
47 #include <dt-bindings/clock/zx296718-clock.h>
51 #address-cells = <1>;
52 #size-cells = <1>;
53 interrupt-parent = <&gic>;
67 #address-cells = <2>;
68 #size-cells = <0>;
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/linux-5.10/Documentation/ABI/testing/
Dsysfs-bus-iio3 Contact: linux-iio@vger.kernel.org
11 Contact: linux-iio@vger.kernel.org
25 Contact: linux-iio@vger.kernel.org
31 Contact: linux-iio@vger.kernel.org
38 Contact: linux-iio@vger.kernel.org
48 Contact: linux-iio@vger.kernel.org
65 Contact: linux-iio@vger.kernel.org
70 - a small discrete set of values like "0 2 4 6 8"
71 - a range with minimum, step and maximum frequencies like
76 Contact: linux-iio@vger.kernel.org
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/linux-5.10/drivers/net/usb/
Dsmsc95xx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2007-2008 SMSC
38 /* SCSRs - System Control and Status Registers */
57 #define INT_STS_TDFU_ (0x00002000) /* TX Data FIFO Underrun */
58 #define INT_STS_TDFO_ (0x00001000) /* TX Data FIFO Overrun */
65 #define RX_FIFO_FLUSH_ (0x00000001) /* Receive FIFO Flush */
71 #define TX_CFG_FIFO_FLUSH_ (0x00000001) /* Transmit FIFO Flush */
88 /* Receive FIFO Information Register */
90 #define RX_FIFO_INF_USED_ (0x0000FFFF) /* RX Data FIFO Used Space */
92 /* Transmit FIFO Information Register */
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/linux-5.10/sound/soc/fsl/
Dfsl_dma.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
16 #include <linux/dma-mapping.h>
72 /** fsl_dma_private: p-substream DMA data
74 * Each substream has a 1-to-1 association with a DMA channel.
76 * The link[] array is first because it needs to be aligned on a 32-byte
120 * Since each link descriptor has a 32-bit byte count field, we set
121 * period_bytes_max to the largest 32-bit number. We also have no maximum
137 .period_bytes_max = (u32) -1,
139 .periods_max = (unsigned int) -1,
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Dfsl_ssi.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
12 // sane processor vendors have a FIFO per AC97 slot, the i.MX has only
13 // one FIFO which combines all valid receive slots. We cannot even select
16 // we receive in our (PCM-) data stream. The only chance we have is to
52 #include "imx-pcm.h"
54 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
64 * order. The STX is a shift register, so all the bits need to be aligned
65 * (bit-endianness must match byte-endianness). Processors typically write
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/linux-5.10/drivers/i2c/busses/
Di2c-fsi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * FSI-attached I2C master algorithm
71 /* watermark register */
189 u32 mode = I2C_MODE_ENHANCED, extended_status, watermark; in fsi_i2c_dev_init() local
193 rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_INT_MASK, &interrupt); in fsi_i2c_dev_init()
198 rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_MODE, &mode); in fsi_i2c_dev_init()
202 rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_ESTAT, &extended_status); in fsi_i2c_dev_init()
206 i2c->fifo_size = FIELD_GET(I2C_ESTAT_FIFO_SZ, extended_status); in fsi_i2c_dev_init()
207 watermark = FIELD_PREP(I2C_WATERMARK_HI, in fsi_i2c_dev_init()
208 i2c->fifo_size - I2C_FIFO_HI_LVL); in fsi_i2c_dev_init()
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/linux-5.10/drivers/net/ethernet/broadcom/
Db44.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */
41 #define ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */
42 #define ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */
65 #define MAC_FLOW_RX_HI_WATER 0x000000ff /* Receive FIFO HI Water Mark */
90 #define DMATX_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */
110 #define DMARX_STAT_EDFO 0x00020000 /* Error Data FIFO Overflow */
113 #define B44_DMAFIFO_AD 0x0220UL /* DMA FIFO Diag Address */
120 #define DMAFIFO_AD_SXFD 0x00080000 /* Select Transmit FIFO Data */
121 #define DMAFIFO_AD_SXFP 0x00090000 /* Select Transmit FIFO Pointers */
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/linux-5.10/drivers/mmc/host/
Ddw_mmc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <linux/dma-mapping.h>
37 #include <linux/mmc/slot-gpio.h>
72 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
77 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
78 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
80 u32 des6; /* Lower 32-bits of Next Descriptor Address */
81 u32 des7; /* Upper 32-bits of Next Descriptor Address */
96 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
109 struct dw_mci_slot *slot = s->private; in dw_mci_req_show()
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/linux-5.10/drivers/tty/serial/
Dserial-tegra.c1 // SPDX-License-Identifier: GPL-2.0
5 * High-speed serial driver for NVIDIA Tegra SoCs
7 * Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved.
16 #include <linux/dma-mapping.h>
57 * Tx fifo trigger level setting in tegra uart is in
80 * @tx_fifo_full_status: Status flag available for checking tx fifo full.
81 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.
155 return readl(tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_read()
161 writel(val, tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_write()
174 * RI - Ring detector is active in tegra_uart_get_mctrl()
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/linux-5.10/drivers/iio/adc/
Dat91-sama5d2_adc.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/dma-mapping.h>
98 /* Interrupt Enable Register - TS X measurement ready */
100 /* Interrupt Enable Register - TS Y measurement ready */
102 /* Interrupt Enable Register - TS pressure measurement ready */
104 /* Interrupt Enable Register - Data ready */
106 /* Interrupt Enable Register - general overrun error */
108 /* Interrupt Enable Register - Pen detect */
110 /* Interrupt Enable Register - No pen detect */
118 /* Interrupt Status Register - Pen touching sense status */
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/linux-5.10/drivers/spi/
Dspi-geni-qcom.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
12 #include <linux/qcom-geni-se.h>
97 ret = geni_se_clk_freq_match(&mas->se, in get_spi_clk_cfg()
98 speed_hz * mas->oversampling, in get_spi_clk_cfg()
101 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n", in get_spi_clk_cfg()
106 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz); in get_spi_clk_cfg()
107 actual_hz = sclk_freq / (mas->oversampling * *clk_div); in get_spi_clk_cfg()
109 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, in get_spi_clk_cfg()
111 ret = dev_pm_opp_set_rate(mas->dev, sclk_freq); in get_spi_clk_cfg()
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/linux-5.10/drivers/net/wireless/intel/iwlwifi/
Diwl-trans.h8 * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
11 * Copyright(c) 2018 - 2019 Intel Corporation
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
34 * Copyright(c) 2018 - 2019 Intel Corporation
72 #include "iwl-debug.h"
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/linux-5.10/include/linux/iio/
Diio.h1 /* SPDX-License-Identifier: GPL-2.0-only */
37 * struct iio_chan_spec_ext_info - Extended channel info attribute
56 * struct iio_enum - Enum channel info attribute
87 * IIO_ENUM() - Initialize enum extended channel attribute
104 * IIO_ENUM_AVAILABLE() - Initialize enum available extended channel attribute
120 * struct iio_mount_matrix - iio mounting matrix
138 * IIO_MOUNT_MATRIX() - Initialize mount matrix extended channel attribute
151 * struct iio_event_spec - specification for a channel event
174 * struct iio_chan_spec - specification of a single channel
222 * @datasheet_name: A name used in in-kernel mapping of channels. It should
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/linux-5.10/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
Dsdio.c1 // SPDX-License-Identifier: ISC
42 /* watermark expressed in number of words */
72 __le32 buf; /* Can't be pointer on (64-bit) hosts */
117 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
118 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
148 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
151 /* 1: enable F2 Watermark */
153 /* Force SD->SB reset mapping (rev 11) */
221 #define I_RO (1 << 14) /* Receive fifo Overflow */
222 #define I_XU (1 << 15) /* Transmit fifo Underflow */
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