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Searched +full:dp +full:- +full:phy0 (Results 1 – 22 of 22) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sm8550-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Neil Armstrong <neil.armstrong@linaro.org>
18 - include/dt-bindings/clock/qcom,sm8550-dispcc.h
19 - include/dt-bindings/clock/qcom,sm8650-dispcc.h
20 - include/dt-bindings/clock/qcom,sm8750-dispcc.h
21 - include/dt-bindings/clock/qcom,x1e80100-dispcc.h
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H A Dqcom,milos-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,milos-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Luca Weiss <luca.weiss@fairphone.com>
16 See also: include/dt-bindings/clock/qcom,milos-dispcc.h
20 const: qcom,milos-dispcc
24 - description: Board XO source
25 - description: Sleep clock source
26 - description: Display's AHB clock
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H A Dqcom,sm7150-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm7150-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Danila Tikhonov <danila@jiaxyga.com>
11 - David Wronek <david@mainlining.org>
12 - Jens Reidel <adrian@travitia.xyz>
18 See also: include/dt-bindings/clock/qcom,sm7150-dispcc.h
22 const: qcom,sm7150-dispcc
26 - description: Board XO source
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H A Dqcom,dispcc-sm6125.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Martin Botka <martin.botka@somainline.org>
16 See also: include/dt-bindings/clock/qcom,dispcc-sm6125.h
21 - qcom,sm6125-dispcc
25 - description: Board XO source
26 - description: Byte clock from DSI PHY0
27 - description: Pixel clock from DSI PHY0
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/linux/Documentation/devicetree/bindings/display/xlnx/
H A Dxlnx,zynqmp-dpsub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 +------------------------------------------------------------+
15 +--------+ | +----------------+ +-----------+ |
16 | DPDMA | --->| | --> | Video | Video +-------------+ |
17 | 4x vid | | | | | Rendering | -+--> | | | +------+
18 | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 |
19 +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+
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/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-sck-kv-g-revB.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16 /dts-v1/;
20 compatible = "xlnx,zynqmp-sk-kv260-rev2",
21 "xlnx,zynqmp-sk-kv260-rev1",
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H A Dzynqmp-sck-kv-g-revA.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
9 * "A" - A01 board un-modified (NXP)
10 * "Y" - A01 board modified with legacy interposer (Nexperia)
11 * "Z" - A01 board modified with Diode interposer
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/net/ti-dp83867.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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H A Dzynqmp-zc1751-xm015-dc1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 model = "ZynqMP zc1751-xm015-dc1 RevA";
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H A Dzynqmp-zcu104-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
21 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
38 stdout-path = "serial0:115200n8";
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H A Dzynqmp-zcu104-revC.dts1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
21 compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
38 stdout-path = "serial0:115200n8";
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H A Dzynqmp-zcu111-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
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H A Dzynqmp-zcu102-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
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/linux/drivers/net/dsa/qca/
H A Dar9331.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * +----------------------+
5 * GMAC1----RGMII----|--MAC0 |
6 * \---MDIO1----|--REGs |----MDIO3----\
7 * | | | +------+
8 * | | +--| |
9 * | MAC1-|----RMII--M-----| PHY0 |-o P0
10 * | | | | +------+
11 * | | | +--| |
12 * | MAC2-|----RMII--------| PHY1 |-o P1
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpio_phy.c2 * Copyright © 2014-2016 Intel Corporation
42 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
48 * IOSF-SB port.
52 * logic. CH0 common lane also contains the IOSF-SB logic for the
62 * each spline is made up of one Physical Access Coding Sub-Layer
64 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
68 * for each channel. This is used for DP AUX communication, but
106 * ---------------------------------
109 * |---------------|---------------| Display PHY
111 * |-------|-------|-------|-------|
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/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721e-beagleboneai64.dts1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * https://beagleboard.org/ai-64
4 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
5 * Copyright (C) 2022-2024 Jason Kridner, BeagleBoard.org Foundation
6 * Copyright (C) 2022-2024 Robert Nelson, BeagleBoard.org Foundation
9 /dts-v1/;
11 #include "k3-j721e.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/leds/common.h>
[all …]
H A Dk3-j721e-sk.dts1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
5 * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM
8 /dts-v1/;
10 #include "k3-j721e.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/net/ti-dp83867.h>
16 compatible = "ti,j721e-sk", "ti,j721e";
29 stdout-path = "serial2:115200n8";
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H A Dk3-j784s4-j742s2-evm-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
9 #include <dt-bindings/phy/phy-cadence.h>
13 stdout-path = "serial2:115200n8";
28 reserved_memory: reserved-memory {
29 #address-cells = <2>;
30 #size-cells = <2>;
35 no-map;
38 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
39 compatible = "shared-dma-pool";
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/linux/arch/arm64/boot/dts/renesas/
H A Dgray-hawk-single.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
6 * Copyright (C) 2024-2025 Glider bv
11 * Because R-Car V4M has only 1 SSI, it cannot handle both Playback/Capture
28 #include <dt-bindings/gpio/gpio.h>
29 #include <dt-bindings/input/input.h>
30 #include <dt-bindings/leds/common.h>
31 #include <dt-bindings/media/video-interfaces.h>
35 compatible = "renesas,gray-hawk-single";
49 can_transceiver0: can-phy0 {
51 #phy-cells = <0>;
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/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588s-coolpi-4b.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * https://cool-pi.com/topic/130/coolpi-4b-product-spec-introduction
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/pinctrl/rockchip.h>
14 #include <dt-bindings/soc/rockchip,vop2.h>
19 compatible = "coolpi,pi-4b", "rockchip,rk3588s";
27 analog-sound {
28 compatible = "audio-graph-card";
[all …]
/linux/drivers/gpu/drm/bridge/
H A Dtc358767.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TC358767/TC358867/TC9595 DSI/DPI-to-DPI/(e)DP bridge driver
6 * All modes are supported -- DPI->(e)DP / DSI->DPI / DSI->(e)DP .
27 #include <linux/media-bus-format.h>
44 /* DSI D-PHY Layer registers */
77 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
110 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
184 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
290 #define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */
295 #define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */
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/linux/drivers/gpu/drm/xlnx/
H A Dzynqmp_disp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
19 #include <linux/dma-mapping.h>
21 #include <linux/media-bus-format.h>
34 * --------
36 * The display controller part of ZynqMP DP subsystem, made of the Audio/Video
39 * +------------------------------------------------------------+
40 * +--------+ | +----------------+ +-----------+ |
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/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192du/
H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0
84 /* channels 1-14. */
89 /* channels 36-64 */
95 /* channels 100-165 */
165 if (rtlhal->during_mac1init_radioa) in rtl92du_phy_query_bb_reg()
167 else if (rtlhal->during_mac0init_radiob) in rtl92du_phy_query_bb_reg()
190 if (rtlhal->during_mac1init_radioa) in rtl92du_phy_set_bb_reg()
192 else if (rtlhal->during_mac0init_radiob) in rtl92du_phy_set_bb_reg()
245 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) { in rtl92du_phy_mac_config()
246 /* improve 2-stream TX EVM */ in rtl92du_phy_mac_config()
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