Home
last modified time | relevance | path

Searched full:downstream (Results 1 – 25 of 384) sorted by relevance

12345678910>>...16

/linux/Documentation/devicetree/bindings/usb/
H A Daspeed,usb-vhub.yaml16 the Virtual Hub's downstream USB devices.
19 revisions. AST2400 and AST2500 Virtual Hub supports 5 downstream devices
20 and 15 generic endpoints, while AST2600 Virtual Hub supports 7 downstream
39 aspeed,vhub-downstream-ports:
40 description: Number of downstream ports supported by the Virtual Hub
107 - aspeed,vhub-downstream-ports
120 aspeed,vhub-downstream-ports = <5>;
H A Dti,tusb73x0-pci.yaml14 The TUSB7320 supports up to two downstream ports, the TUSB7340 supports up
15 to four downstream ports, both variants share the same PCI device ID.
/linux/Documentation/driver-api/cxl/linux/
H A Dcxl-driver.rst82 * `Downstream Ports` typically connected to `Host Bridge Ports`.
104 only has downstream port connections.
110 contains one or more decoders used to route memory requests downstream ports,
133 * The root has a downstream port connection to a host bridge
137 * The host bridge has one or more downstream port connections to switch
145 upstream and downstream ports.
242 Decoders may have one or more `Downstream Targets` if configured to interleave
275 the *immediate downstream targets*, not the entire interleave set.
300 of `Switch Decoder` due to having downstream targets. ::
323 decoder and downstream target ports. Interleaving done within a switch decoder
[all …]
/linux/drivers/pci/pcie/
H A Daspm.c89 * If this is a Downstream Port, we never restore the L1SS state in pci_save_aspm_l1ss_state()
134 * on the downstream component before the upstream. So, don't attempt to in pci_restore_aspm_l1ss_state()
135 * restore either until we are at the downstream component. in pci_restore_aspm_l1ss_state()
167 * Disable L1.2 on this downstream endpoint device first, followed in pci_restore_aspm_l1ss_state()
216 #define PCIE_LINK_STATE_L0S_DW BIT(1) /* Downstream direction L0s state */
229 struct pci_dev *downstream; /* Downstream component, function 0 */ member
420 /* Check downstream component if bit Slot Clock Configuration is 1 */ in pcie_aspm_configure_common_clock()
450 /* Configure downstream component, all functions */ in pcie_aspm_configure_common_clock()
607 /* Check downstream direction L0s latency */ in pcie_aspm_check_latency()
638 struct pci_dev *child = link->downstream, *parent = link->pdev; in aspm_calc_l12_info()
[all …]
/linux/Documentation/driver-api/cxl/linux/example-configurations/
H A Dintra-hb-interleave.rst46 This chunk shows the CXL "bus" (root0) has 4 downstream ports attached to CXL
50 The `ports:root0` section lays out how each of these downstream ports are
79 This chunk shows the available downstream ports associated with the CXL Host
80 Bridge :code:`port1`. In this case, :code:`port1` has 3 available downstream
234 applies the interleave across the downstream ports :code:`port1` and
H A Dhb-interleave.rst46 This chunk shows the CXL "bus" (root0) has 4 downstream ports attached to CXL
50 The `ports:root0` section lays out how each of these downstream ports are
79 This chunk shows the available downstream ports associated with the CXL Host
80 Bridge :code:`port1`. In this case, :code:`port1` has 3 available downstream
250 applies the interleave across the downstream ports :code:`port1` and
H A Dsingle-device.rst46 This chunk shows the CXL "bus" (root0) has 4 downstream ports attached to CXL
50 The `ports:root0` section lays out how each of these downstream ports are
79 This chunk shows the available downstream ports associated with the CXL Host
80 Bridge :code:`port1`. In this case, :code:`port1` has 3 available downstream
H A Dmulti-interleave.rst47 This chunk shows the CXL "bus" (root0) has 4 downstream ports attached to CXL
51 The `ports:root0` section lays out how each of these downstream ports are
80 This chunk shows the available downstream ports associated with the CXL Host
81 Bridge :code:`port1`. In this case, :code:`port1` has 3 available downstream
326 applies the interleave across the downstream ports :code:`port1` and
/linux/drivers/thunderbolt/
H A Dtb.c529 /* Find the downstream USB4 port that leads to this router */ in tb_find_first_usb3_tunnel()
531 /* Find the corresponding host router USB3 downstream port */ in tb_find_first_usb3_tunnel()
546 * @consumed_down: Consumed downstream bandwidth (Mb/s)
595 * @consumed_down: Consumed downstream bandwidth (Mb/s)
615 bool downstream; in tb_consumed_dp_bandwidth() local
664 downstream = tb_port_path_direction_downstream(src_port, dst_port); in tb_consumed_dp_bandwidth()
666 if (downstream) in tb_consumed_dp_bandwidth()
678 bool downstream = tb_port_path_direction_downstream(src_port, dst_port); in tb_asym_supported() local
682 width = downstream ? TB_LINK_WIDTH_ASYM_RX : TB_LINK_WIDTH_ASYM_TX; in tb_asym_supported()
684 width = downstream ? TB_LINK_WIDTH_ASYM_TX : TB_LINK_WIDTH_ASYM_RX; in tb_asym_supported()
[all …]
H A Dacpi.c44 /* Check that this matches a PCIe root/downstream port. */ in tb_acpi_add_link()
291 * Device routers exists under the downstream facing USB4 port in tb_acpi_switch_find_companion()
321 * Device (DFP0) // Downstream port _ADR == lane 0 adapter in tb_acpi_find_companion()
324 * Device (DFP1) // Downstream port _ADR == lane 0 adapter number in tb_acpi_find_companion()
/linux/include/linux/
H A Di2c-atr.h55 * struct i2c_atr_adap_desc - An ATR downstream bus descriptor
106 * i2c_atr_add_adapter - Create a child ("downstream") I2C bus.
111 * devices on the downstream bus will result in calls to the
126 * i2c_atr_del_adapter - Remove a child ("downstream") I2C bus added by
/linux/include/uapi/linux/usb/
H A Dcharger.h11 * SDP (Standard Downstream Port)
13 * CDP (Charging Downstream Port)
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls2080a.dtsi141 ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
149 ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
157 ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
165 ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
/linux/arch/arm/mach-omap2/
H A Dclockdomain.c938 * into active or idle states, as needed by downstream clocks. If the
939 * clockdomain has any downstream clocks enabled in the clock
980 * active or idle states, as needed by downstream clocks. If the
981 * clockdomain has any downstream clocks enabled in the clock
998 * downstream clocks enabled in the clock framework, wkdep/sleepdep
1036 * downstream clocks enabled in the clock framework, wkdep/sleepdep
1111 * clkdm_clk_enable - add an enabled downstream clock to this clkdm
1113 * @unused: struct clk * of the enabled downstream clock
1152 * clkdm_clk_disable - remove an enabled downstream clock from this clkdm
1154 * @clk: struct clk * of the disabled downstream clock
[all …]
/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-atr.yaml14 ("upstream") port and N I2C master child ("downstream") ports, and
15 forwards transactions from upstream to the appropriate downstream port
H A Di2c-mux-ltc4306.txt24 - ltc,downstream-accelerators-enable: Enables the rise time accelerators
25 on the downstream port.
/linux/Documentation/ABI/testing/
H A Dusb-charger-uevent14 USB_CHARGER_SDP_TYPE Standard Downstream Port
15 USB_CHARGER_CDP_TYPE Charging Downstream Port
H A Dsysfs-bus-usb-lvstest16 Set "U1 timeout" for the downstream port where Link Layer
24 Set "U2 timeout" for the downstream port where Link Layer
/linux/Documentation/devicetree/bindings/misc/
H A Dti,fpc202.yaml41 description: Downstream device ports 0 and 1
47 Downstream port ID
/linux/drivers/media/pci/cx88/
H A Dcx88-reg.h213 #define MO_AUDD_DMA 0x320000 // {64}RWp Audio downstream
215 #define MO_AUDR_DMA 0x320010 // {64}RWp Audio RDS (downstream)
433 #define MO_TS_DMA 0x330000 // {64}RWp Transport stream downstream
451 #define MO_VIPD_DMA 0x340000 // {64}RWp VIP downstream
461 #define MO_VIPD_CNTRL 0x340050 // VIP downstream control #2
462 #define MO_VIPD_LNGTH 0x340054 // VIP downstream line length
519 #define MO_GPHSTD_DMA 0x350000 // {64}RWp Host downstream
522 #define MO_GPHSTD_CNTRL 0x38004C // Host downstream control #2
523 #define MO_GPHSTD_LNGTH 0x380050 // Host downstream line length
/linux/drivers/clk/sophgo/
H A Dclk-sg2042-clkgen.c423 * from top to bottom, from upstream to downstream. Read TRM for details.
604 /* downstream of div_50m_a53 */
646 /* downstream of div_top_axi0 */
681 /* upon are gate clocks directly downstream of muxes */
683 /* downstream of clk_div_top_rp_cmn_div2 */
691 * downstream of clk_gate_rp_cpu_normal
707 /* downstream of div_50m_a53 */
727 /* gate clocks downstream from div clocks one-to-one */
746 /* downstream of clk_div_top_axi0 */
773 /* downstream of DIV clocks which are sourced from clk_div_top_axi0 */
[all …]
/linux/include/cxl/
H A Devent.h216 RCH_DP, /* Restricted CXL Host Downstream Port */
221 DSP, /* CXL Downstream Switch Port */
234 * Except for RCH Downstream Port, all the remaining CXL Agent
/linux/Documentation/devicetree/bindings/power/supply/
H A Dgpio-charger.yaml27 - usb-sdp # USB standard downstream port
29 - usb-cdp # USB charging downstream port
/linux/Documentation/devicetree/bindings/display/bridge/
H A Dfsl,imx8qxp-pxl2dpi.yaml37 A phandle which points to companion PXL2DPI which is used by downstream
50 description: The PXL2DPI output port node to downstream bridge.
/linux/drivers/net/ipa/data/
H A Dipa_data-v3.1.c265 .min = 5, .max = 5, /* 3 downstream */
268 .min = 5, .max = 5, /* 7 downstream */
331 .min = 3, .max = 3, /* 2 downstream */
337 .min = 1, .max = 1, /* 0 downstream */
339 /* IPA_RSRC_GROUP_DST_DMA uses 2 downstream */

12345678910>>...16