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/linux-6.15/drivers/clk/qcom/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
23 tristate "X1E80100 Camera Clock Controller"
27 Support for the camera clock controller on X1E80100 devices.
31 tristate "X1E80100 Display Clock Controller"
35 Support for the two display clock controllers on Qualcomm
37 Say Y if you want to support display devices and functionality such as
41 tristate "X1E80100 Global Clock Controller"
45 Support for the global clock controller on Qualcomm Technologies, Inc
51 tristate "X1E80100 Graphics Clock Controller"
55 Support for the graphics clock controller on X1E80100 devices.
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/linux-6.15/Documentation/gpu/amdgpu/display/
Ddc-glossary.rst5 On this page, we try to keep track of acronyms related to the display
7 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere,
19 Application-Specific Integrated Circuit
37 * DISPCLK: Display Clock
39 * DCFCLK: Display Controller Fabric Clock
49 Cathode Ray Tube Controller - commonly called "Controller" - Generates
56 Display Abstraction layer
59 Display Core
62 Display Controller
68 Display Controller Engine
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/linux-6.15/drivers/staging/fbtft/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 tristate "Support for small TFT LCD display modules"
12 tristate "FB driver for the AGM1264K-FL LCD display"
15 Framebuffer support for the AGM1264K-FL LCD display (two Samsung KS0108 compatible chips)
18 tristate "FB driver for the BD663474 LCD Controller"
24 tristate "FB driver for the HX8340BN LCD Controller"
30 tristate "FB driver for the HX8347D LCD Controller"
36 tristate "FB driver for the HX8353D LCD Controller"
42 tristate "FB driver for the HX8357D LCD Controller"
48 tristate "FB driver for the ILI9163 LCD Controller"
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/linux-6.15/Documentation/devicetree/bindings/auxdisplay/
Dhit,hd44780.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Hitachi HD44780 Character LCD Controller
10 - Geert Uytterhoeven <geert@linux-m68k.org>
13 The Hitachi HD44780 Character LCD Controller is commonly used on character
14 LCDs that can display one or more lines of text. It exposes an M6800 bus
15 interface, which can be used in either 4-bit or 8-bit mode. By using a
24 data-gpios:
26 GPIO pins connected to the data signal lines DB0-DB7 (8-bit mode) or
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/linux-6.15/drivers/gpu/drm/i915/display/
Dintel_backlight.c1 // SPDX-License-Identifier: MIT
28 * scale - scale values from one range to another
52 target_val = mul_u32_u32(source_val - source_min, in scale()
53 target_max - target_min); in scale()
54 target_val = DIV_ROUND_CLOSEST_ULL(target_val, source_max - source_min); in scale()
67 struct intel_panel *panel = &connector->panel; in clamp_user_to_hw()
70 hw_level = scale(user_level, 0, user_max, 0, panel->backlight.max); in clamp_user_to_hw()
71 hw_level = clamp(hw_level, panel->backlight.min, panel->backlight.max); in clamp_user_to_hw()
80 struct intel_panel *panel = &connector->panel; in scale_hw_to_user()
82 return scale(hw_level, panel->backlight.min, panel->backlight.max, in scale_hw_to_user()
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/linux-6.15/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra186-dc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) Display Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^display@[0-9a-f]+$"
19 - nvidia,tegra186-dc
20 - nvidia,tegra194-dc
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Dnvidia,tegra20-dc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Display Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^dc@[0-9a-f]+$"
19 - enum:
20 - nvidia,tegra20-dc
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/linux-6.15/Documentation/devicetree/bindings/display/
Dapple,h7-display-pipe-mipi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/apple,h7-display-pipe-mipi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple pre-DCP display controller MIPI interface
10 - Sasha Finkelstein <fnkl.kernel@gmail.com>
13 The MIPI controller part of the pre-DCP Apple display controller
16 - $ref: dsi-controller.yaml#
21 - enum:
22 - apple,t8112-display-pipe-mipi
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Dapple,h7-display-pipe.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/apple,h7-display-pipe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple pre-DCP display controller
10 - Sasha Finkelstein <fnkl.kernel@gmail.com>
13 A secondary display controller used to drive the "touchbar" on
19 - enum:
20 - apple,t8112-display-pipe
21 - apple,t8103-display-pipe
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Dxylon,logicvc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Xylon LogiCVC display controller
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
14 The Xylon LogiCVC is a display controller that supports multiple layers.
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
18 Because the controller is intended for use in a FPGA, most of the
19 configuration of the controller takes place at logic configuration bitstream
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Dintel,keembay-display.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/intel,keembay-display.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Keem Bay display controller
10 - Anitha Chrisanthus <anitha.chrisanthus@intel.com>
11 - Edmond J Dea <edmund.j.dea@intel.com>
15 const: intel,keembay-display
19 - description: LCD registers range
21 reg-names:
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/linux-6.15/drivers/gpu/drm/sun4i/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "DRM Support for Allwinner A10 Display Engine"
14 Display Engine. If M is selected the module will be called
15 sun4i-drm.
20 tristate "Allwinner A10/A10s/A20/A31 HDMI Controller Support"
28 SoC with an HDMI controller.
37 SoC with an HDMI controller and want to use CEC.
40 tristate "Support for Allwinner A10 Display Engine Backend"
45 original Allwinner Display Engine, which has a backend to
47 selected the module will be called sun4i-backend.
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/linux-6.15/Documentation/devicetree/bindings/display/msm/
Dqcom,sc8280xp-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SC8280XP Mobile Display Subsystem
10 - Bjorn Andersson <andersson@kernel.org>
13 Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sc8280xp-mdss
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Dqcom,mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Mobile Display SubSystem (MDSS)
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11 - Rob Clark <robdclark@gmail.com>
14 This is the bindings documentation for the Mobile Display Subsystem(MDSS) that
15 encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
19 pattern: "^display-subsystem@[0-9a-f]+$"
[all …]
Dqcom,x1e80100-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,x1e80100-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm X1E80100 Display MDSS
10 - Abel Vesa <abel.vesa@linaro.org>
13 X1E80100 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DP interfaces, etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,x1e80100-mdss
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Dqcom,sm8350-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8350 Display MDSS
10 - Robert Foss <robert.foss@linaro.org>
13 MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like
14 DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
21 - const: qcom,sm8350-mdss
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Dqcom,sa8775p-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sa8775p-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. SA87755P Display MDSS
10 - Mahadevan <quic_mahap@quicinc.com>
13 SA8775P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DP interfaces and EDP etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sa8775p-mdss
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Dqcom,sm6350-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM6350 Display MDSS
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 SM6350 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
14 like DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm6350-mdss
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/linux-6.15/Documentation/devicetree/bindings/mfd/
Datmel,hlcdc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Atmel's HLCD Controller
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Alexandre Belloni <alexandre.belloni@bootlin.com>
12 - Claudiu Beznea <claudiu.beznea@tuxon.dev>
15 The Atmel HLCDC (HLCD Controller) IP available on Atmel SoCs exposes two
16 subdevices, a PWM chip and a Display Controller.
21 - atmel,at91sam9n12-hlcdc
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/linux-6.15/Documentation/gpu/
Dtegra.rst2 drm/tegra NVIDIA Tegra GPU and display driver
5 NVIDIA Tegra SoCs support a set of display, graphics and video functions via
6 the host1x controller. host1x supplies command streams, gathered from a push
11 supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting
18 - A host1x driver that provides infrastructure and access to the host1x
21 - A KMS driver that supports the display controllers as well as a number of
24 - A set of custom userspace IOCTLs that can be used to submit jobs to the
40 device using a driver-provided function which will set up the bits specific to
48 -------------------------------
50 .. kernel-doc:: include/linux/host1x.h
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/linux-6.15/Documentation/devicetree/bindings/display/atmel/
Datmel,hlcdc-display-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/atmel/atmel,hlcdc-display-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Atmel's High LCD Controller (HLCDC)
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Alexandre Belloni <alexandre.belloni@bootlin.com>
12 - Claudiu Beznea <claudiu.beznea@tuxon.dev>
15 The LCD Controller (LCDC) consists of logic for transferring LCD image
16 data from an external display buffer to a TFT LCD panel. The LCDC has one
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/linux-6.15/Documentation/devicetree/bindings/display/panel/
Dpanel-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Display Panels
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
15 display panels. It doesn't constitute a device tree binding specification by
24 width-mm:
29 height-mm:
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/linux-6.15/drivers/video/fbdev/mmp/hw/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "mmp display controller hw support"
7 Marvell MMP display hw controller support
8 this controller is used on Marvell PXA910 and
12 bool "mmp display controller spi port"
16 Marvell MMP display hw controller spi port support
/linux-6.15/drivers/gpu/drm/xlnx/
Dzynqmp_disp.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP Display Controller Driver
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
19 #include <linux/dma-mapping.h>
21 #include <linux/media-bus-format.h>
34 * --------
36 * The display controller part of ZynqMP DP subsystem, made of the Audio/Video
39 * +------------------------------------------------------------+
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/linux-6.15/Documentation/devicetree/bindings/display/samsung/
Dsamsung,exynos7-decon.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos7-decon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos7 SoC Display and Enhancement Controller (DECON)
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
16 DECON (Display and Enhancement Controller) is the Display Controller for the
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