Lines Matching +full:display +full:- +full:controller
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sa8775p-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. SA87755P Display MDSS
10 - Mahadevan <quic_mahap@quicinc.com>
13 SA8775P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DP interfaces and EDP etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sa8775p-mdss
24 - description: Display AHB
25 - description: Display hf AXI
26 - description: Display core
34 interconnect-names:
38 "^display-controller@[0-9a-f]+$":
44 const: qcom,sa8775p-dpu
46 "^displayport-controller@[0-9a-f]+$":
53 - const: qcom,sa8775p-dp
55 "^phy@[0-9a-f]+$":
60 const: qcom,sa8775p-edp-phy
63 - compatible
68 - |
69 #include <dt-bindings/interconnect/qcom,icc.h>
70 #include <dt-bindings/interrupt-controller/arm-gic.h>
71 #include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
72 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
73 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
74 #include <dt-bindings/power/qcom,rpmhpd.h>
75 #include <dt-bindings/power/qcom-rpmpd.h>
77 display-subsystem@ae00000 {
78 compatible = "qcom,sa8775p-mdss";
80 reg-names = "mdss";
85 interconnect-names = "mdp0-mem",
86 "mdp1-mem",
87 "cpu-cfg";
90 power-domains = <&dispcc_gdsc>;
97 interrupt-controller;
98 #interrupt-cells = <1>;
102 #address-cells = <1>;
103 #size-cells = <1>;
106 display-controller@ae01000 {
107 compatible = "qcom,sa8775p-dpu";
110 reg-names = "mdp", "vbif";
117 clock-names = "nrt_bus",
123 assigned-clocks = <&dispcc_mdp_vsync_clk>;
124 assigned-clock-rates = <19200000>;
126 operating-points-v2 = <&mdss0_mdp_opp_table>;
127 power-domains = <&rpmhpd RPMHPD_MMCX>;
129 interrupt-parent = <&mdss0>;
133 #address-cells = <1>;
134 #size-cells = <0>;
139 remote-endpoint = <&mdss0_dp0_in>;
144 mdss0_mdp_opp_table: opp-table {
145 compatible = "operating-points-v2";
147 opp-375000000 {
148 opp-hz = /bits/ 64 <375000000>;
149 required-opps = <&rpmhpd_opp_svs_l1>;
152 opp-500000000 {
153 opp-hz = /bits/ 64 <500000000>;
154 required-opps = <&rpmhpd_opp_nom>;
157 opp-575000000 {
158 opp-hz = /bits/ 64 <575000000>;
159 required-opps = <&rpmhpd_opp_turbo>;
162 opp-650000000 {
163 opp-hz = /bits/ 64 <650000000>;
164 required-opps = <&rpmhpd_opp_turbo_l1>;
170 compatible = "qcom,sa8775p-edp-phy";
179 clock-names = "aux",
182 #clock-cells = <1>;
183 #phy-cells = <0>;
185 vdda-phy-supply = <&vreg_l1c>;
186 vdda-pll-supply = <&vreg_l4a>;
189 displayport-controller@af54000 {
190 compatible = "qcom,sa8775p-dp";
192 pinctrl-0 = <&dp_hot_plug_det>;
193 pinctrl-names = "default";
201 interrupt-parent = <&mdss0>;
209 clock-names = "core_iface",
215 assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
217 assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
220 phy-names = "dp";
222 operating-points-v2 = <&dp_opp_table>;
223 power-domains = <&rpmhpd SA8775P_MMCX>;
225 #sound-dai-cells = <0>;
228 #address-cells = <1>;
229 #size-cells = <0>;
234 remote-endpoint = <&dpu_intf0_out>;
244 dp_opp_table: opp-table {
245 compatible = "operating-points-v2";
247 opp-160000000 {
248 opp-hz = /bits/ 64 <160000000>;
249 required-opps = <&rpmhpd_opp_low_svs>;
252 opp-270000000 {
253 opp-hz = /bits/ 64 <270000000>;
254 required-opps = <&rpmhpd_opp_svs>;
257 opp-540000000 {
258 opp-hz = /bits/ 64 <540000000>;
259 required-opps = <&rpmhpd_opp_svs_l1>;
262 opp-810000000 {
263 opp-hz = /bits/ 64 <810000000>;
264 required-opps = <&rpmhpd_opp_nom>;