Home
last modified time | relevance | path

Searched +full:clk +full:- +full:out +full:- +full:frequency (Results 1 – 25 of 514) sorted by relevance

12345678910>>...21

/linux-5.10/drivers/cpufreq/
Ds3c64xx-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/clk.h>
58 old_freq = clk_get_rate(policy->clk) / 1000; in s3c64xx_cpufreq_set_target()
59 new_freq = s3c64xx_freq_table[index].frequency; in s3c64xx_cpufreq_set_target()
65 dvfs->vddarm_min, in s3c64xx_cpufreq_set_target()
66 dvfs->vddarm_max); in s3c64xx_cpufreq_set_target()
75 ret = clk_set_rate(policy->clk, new_freq * 1000); in s3c64xx_cpufreq_set_target()
85 dvfs->vddarm_min, in s3c64xx_cpufreq_set_target()
86 dvfs->vddarm_max); in s3c64xx_cpufreq_set_target()
90 if (clk_set_rate(policy->clk, old_freq * 1000) < 0) in s3c64xx_cpufreq_set_target()
[all …]
Ds3c24xx-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2006-2008 Simtec Electronics
7 * S3C24XX CPU Frequency scaling
18 #include <linux/clk.h>
24 #include <linux/soc/samsung/s3c-cpufreq-core.h>
25 #include <linux/soc/samsung/s3c-pm.h>
39 static struct clk *_clk_mpll;
40 static struct clk *_clk_xtal;
41 static struct clk *clk_fclk;
42 static struct clk *clk_hclk;
[all …]
Dvexpress-spc-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013 - 2019 ARM Ltd.
14 #include <linux/clk.h>
51 static struct clk *clk[MAX_CLUSTERS]; variable
56 static unsigned int clk_little_max; /* Maximum clock frequency (Little) */
93 u32 rate = clk_get_rate(clk[cur_cluster]) / 1000; in clk_get_cpu_rate()
130 ret = clk_set_rate(clk[new_cluster], new_rate * 1000); in ve_spc_cpufreq_set_rate()
136 * current design of the clk core layer. To work around this in ve_spc_cpufreq_set_rate()
138 * correct. This needs to be removed once clk core is fixed. in ve_spc_cpufreq_set_rate()
140 if (clk_get_rate(clk[new_cluster]) != new_rate * 1000) in ve_spc_cpufreq_set_rate()
[all …]
Ds3c2416-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <linux/clk.h>
25 struct clk *armdiv;
26 struct clk *armclk;
27 struct clk *hclk;
47 /* pseudo-frequency for dvs mode */
50 /* frequency to sleep and reboot in
61 /* S3C2416 only supports changing the voltage in the dvs-mode.
94 /* return our pseudo-frequency when in dvs mode */ in s3c2416_cpufreq_get_speed()
95 if (s3c_freq->is_dvs) in s3c2416_cpufreq_get_speed()
[all …]
Darmada-37xx-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0+
3 * CPU frequency scaling support for Armada 37xx platform.
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 #include <linux/clk.h>
26 #include "cpufreq-dt.h"
114 pr_err("Unsupported CPU frequency %d MHz\n", freq/1000000); in armada_37xx_cpu_freq_info_get()
123 struct clk *clk, u8 *divider) in armada37xx_cpufreq_dvfs_setup() argument
126 struct clk *parent; in armada37xx_cpufreq_dvfs_setup()
146 * Set cpu divider based on the pre-computed array in in armada37xx_cpufreq_dvfs_setup()
169 parent = clk_get_parent(clk); in armada37xx_cpufreq_dvfs_setup()
[all …]
/linux-5.10/Documentation/devicetree/bindings/net/
Dqca,ar803x.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
21 qca,clk-out-frequency:
22 description: Clock output frequency in Hertz.
26 qca,clk-out-strength:
[all …]
/linux-5.10/arch/arm/kernel/
Dsmp_twd.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
28 static struct clk *twd_clk;
37 static int twd_shutdown(struct clock_event_device *clk) in twd_shutdown() argument
43 static int twd_set_oneshot(struct clock_event_device *clk) in twd_set_oneshot() argument
51 static int twd_set_periodic(struct clock_event_device *clk) in twd_set_periodic() argument
94 struct clock_event_device *clk = raw_cpu_ptr(twd_evt); in twd_timer_stop() local
96 twd_shutdown(clk); in twd_timer_stop()
97 disable_percpu_irq(clk->irq); in twd_timer_stop()
101 * Updates clockevent frequency when the cpu frequency changes.
[all …]
/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgm20b.c19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 #include <subdev/clk.h>
89 #define DFS_DET_RANGE 6 /* -2^6 ... 2^6-1 */
90 #define SDM_DIN_RANGE 12 /* -2^12 ... 2^12-1 */
99 .coeff_slope = -165230,
136 /* safe frequency we can use at minimum voltage */
160 gm20b_pllg_read_mnp(struct gm20b_clk *clk, struct gm20b_pll *pll) in gm20b_pllg_read_mnp() argument
162 struct nvkm_subdev *subdev = &clk->base.base.subdev; in gm20b_pllg_read_mnp()
163 struct nvkm_device *device = subdev->device; in gm20b_pllg_read_mnp()
166 gk20a_pllg_read_mnp(&clk->base, &pll->base); in gm20b_pllg_read_mnp()
[all …]
/linux-5.10/drivers/sh/clk/
Dcore.c4 * Copyright (C) 2005 - 2010 Paul Mundt
8 * Copyright (C) 2004 - 2008 Nokia Corporation
29 #include <linux/clk.h>
39 void clk_rate_table_build(struct clk *clk, in clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
55 if (src_table->divisors && i < src_table->nr_divisors) in clk_rate_table_build()
56 div = src_table->divisors[i]; in clk_rate_table_build()
58 if (src_table->multipliers && i < src_table->nr_multipliers) in clk_rate_table_build()
59 mult = src_table->multipliers[i]; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
[all …]
/linux-5.10/drivers/pwm/
Dpwm-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/clk.h>
41 * Maximum control word value allowed when variable-frequency PWM is used as a
42 * clock for the constant-frequency PMW.
57 struct clk *clk; member
65 return __raw_readl(p->base + offset); in brcmstb_pwm_readl()
67 return readl_relaxed(p->base + offset); in brcmstb_pwm_readl()
74 __raw_writel(value, p->base + offset); in brcmstb_pwm_writel()
76 writel_relaxed(value, p->base + offset); in brcmstb_pwm_writel()
85 * Fv is derived from the variable frequency output. The variable frequency
[all …]
/linux-5.10/drivers/i2c/busses/
Di2c-s3c2410.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* linux/drivers/i2c/busses/i2c-s3c2410.c
22 #include <linux/clk.h>
34 #include <linux/platform_data/i2c-s3c2410.h>
111 struct clk *clk; member
127 .name = "s3c2410-i2c",
130 .name = "s3c2440-i2c",
133 .name = "s3c2440-hdmiphy-i2c",
143 { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
144 { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
[all …]
Di2c-digicolor.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
50 struct clk *clk; member
51 unsigned int frequency; member
73 writeb_relaxed(cmd | II_COMMAND_GO, i2c->regs + II_COMMAND); in dc_i2c_cmd()
78 u8 addr = (msg->addr & 0x7f) << 1; in dc_i2c_addr_cmd()
80 if (msg->flags & I2C_M_RD) in dc_i2c_addr_cmd()
88 writeb_relaxed(data, i2c->regs + II_DATA); in dc_i2c_data()
99 dc_i2c_write_byte(i2c, i2c->msg->buf[i2c->msgbuf_ptr++]); in dc_i2c_write_buf()
104 bool last = (i2c->msgbuf_ptr + 1 == i2c->msg->len); in dc_i2c_next_read()
[all …]
Di2c-efm32.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Uwe Kleine-Koenig for Pengutronix
11 #include <linux/clk.h>
13 #define DRIVER_NAME "efm32-i2c"
114 struct clk *clk; member
118 unsigned long frequency; member
130 return readl(ddata->base + offset); in efm32_i2c_read32()
136 writel(value, ddata->base + offset); in efm32_i2c_write32()
141 struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg]; in efm32_i2c_send_next_msg()
149 struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg]; in efm32_i2c_send_next_byte()
[all …]
/linux-5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
Ddcn30_clk_mgr_smu_msg.c19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 CTX->logger
65 } while (max_retries--); in dcn30_smu_wait_for_response()
199 /* Returns the actual frequency that was set in MHz, 0 on failure */
200 unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint16_t… in dcn30_smu_set_hard_min_by_freq() argument
204 /* bits 23:16 for clock type, lower 16 bits for frequency in MHz */ in dcn30_smu_set_hard_min_by_freq()
205 uint32_t param = (clk << 16) | freq_mhz; in dcn30_smu_set_hard_min_by_freq()
207 smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz); in dcn30_smu_set_hard_min_by_freq()
212 smu_print("SMU Frequency set = %d MHz\n", response); in dcn30_smu_set_hard_min_by_freq()
217 /* Returns the actual frequency that was set in MHz, 0 on failure */
[all …]
/linux-5.10/drivers/clocksource/
Dmps2-timer.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
51 writel_relaxed(val, to_mps2_clkevt(c)->reg + offset); in clockevent_mps2_writel()
72 u32 clock_count_per_tick = to_mps2_clkevt(ce)->clock_count_per_tick; in mps2_timer_set_periodic()
84 u32 status = readl_relaxed(ce->reg + TIMER_INT); in mps2_timer_interrupt()
91 writel_relaxed(1, ce->reg + TIMER_INT); in mps2_timer_interrupt()
93 ce->clkevt.event_handler(&ce->clkevt); in mps2_timer_interrupt()
101 struct clk *clk = NULL; in mps2_clockevent_init() local
105 const char *name = "mps2-clkevt"; in mps2_clockevent_init()
107 ret = of_property_read_u32(np, "clock-frequency", &rate); in mps2_clockevent_init()
[all …]
Darm_arch_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
93 struct clock_event_device *clk) in arch_timer_reg_write() argument
96 struct arch_timer *timer = to_arch_timer(clk); in arch_timer_reg_write()
99 writel_relaxed(val, timer->base + CNTP_CTL); in arch_timer_reg_write()
102 writel_relaxed(val, timer->base + CNTP_TVAL); in arch_timer_reg_write()
106 struct arch_timer *timer = to_arch_timer(clk); in arch_timer_reg_write()
109 writel_relaxed(val, timer->base + CNTV_CTL); in arch_timer_reg_write()
112 writel_relaxed(val, timer->base + CNTV_TVAL); in arch_timer_reg_write()
122 struct clock_event_device *clk) in arch_timer_reg_read() argument
127 struct arch_timer *timer = to_arch_timer(clk); in arch_timer_reg_read()
[all …]
/linux-5.10/arch/arm/boot/dts/
Dmps2.dtsi6 * This file is dual-licensed: you can use it either under the terms
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 #include "armv7-m.dtsi"
48 #address-cells = <1>;
49 #size-cells = <1>;
51 oscclk0: clk-osc0 {
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <50000000>;
57 oscclk1: clk-osc1 {
[all …]
/linux-5.10/drivers/clk/sunxi-ng/
Dccu_mux.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
22 if (!((common->features & CCU_FEATURE_FIXED_PREDIV) || in ccu_mux_get_prediv()
23 (common->features & CCU_FEATURE_VARIABLE_PREDIV) || in ccu_mux_get_prediv()
24 (common->features & CCU_FEATURE_ALL_PREDIV))) in ccu_mux_get_prediv()
27 if (common->features & CCU_FEATURE_ALL_PREDIV) in ccu_mux_get_prediv()
28 return common->prediv; in ccu_mux_get_prediv()
30 reg = readl(common->base + common->reg); in ccu_mux_get_prediv()
[all …]
/linux-5.10/sound/soc/sh/rcar/
Dadg.c1 // SPDX-License-Identifier: GPL-2.0
3 // Helper routines for R-Car sound ADG.
7 #include <linux/clk-provider.h>
29 struct clk *clk[CLKMAX]; member
30 struct clk *clkout[CLKOUTMAX];
49 ((pos) = adg->clk[i]); \
54 ((pos) = adg->clkout[i]); \
56 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
72 for (i = 3; i >= 0; i--) { in rsnd_adg_calculate_rbgx()
75 return (u32)((i << 8) | ((div / ratio) - 1)); in rsnd_adg_calculate_rbgx()
[all …]
/linux-5.10/drivers/clk/ti/
Ddpll44xx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP4-specific DPLL control functions
11 #include <linux/clk.h>
14 #include <linux/clk/ti.h>
19 * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
20 * can supported when using the DPLL low-power mode. Frequencies are
22 * Status, and Low-Power Operation Mode".
37 static void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) in omap4_dpllmx_allow_gatectrl() argument
42 if (!clk) in omap4_dpllmx_allow_gatectrl()
45 mask = clk->flags & CLOCK_CLKOUTX2 ? in omap4_dpllmx_allow_gatectrl()
[all …]
/linux-5.10/drivers/clk/at91/
Ddt-compat.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
3 #include <linux/clk/at91_pmc.h>
31 const char *name = np->name; in of_sama5d2_clk_audio_pll_frac_setup()
48 "atmel,sama5d2-clk-audio-pll-frac",
54 const char *name = np->name; in of_sama5d2_clk_audio_pll_pad_setup()
71 "atmel,sama5d2-clk-audio-pll-pad",
77 const char *name = np->name; in of_sama5d2_clk_audio_pll_pmc_setup()
94 "atmel,sama5d2-clk-audio-pll-pmc",
148 if (of_property_read_string(np, "clock-output-names", &name)) in of_sama5d2_clk_generated_setup()
[all …]
/linux-5.10/Documentation/devicetree/bindings/spi/
Dnvidia,tegra114-spi.txt4 - compatible : For Tegra114, must contain "nvidia,tegra114-spi".
5 Otherwise, must contain '"nvidia,<chip>-spi", "nvidia,tegra114-spi"' where
7 - reg: Should contain SPI registers location and length.
8 - interrupts: Should contain SPI interrupts.
9 - clock-names : Must include the following entries:
10 - spi
11 - resets : Must contain an entry for each entry in reset-names.
13 - reset-names : Must include the following entries:
14 - spi
15 - dmas : Must contain an entry for each entry in clock-names.
[all …]
/linux-5.10/arch/arm/mach-omap1/
Dclock.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap1/clock.c
5 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
17 #include <linux/clk.h>
20 #include <asm/mach-types.h>
31 struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
41 unsigned long omap1_uart_recalc(struct clk *clk) in omap1_uart_recalc() argument
43 unsigned int val = __raw_readl(clk->enable_reg); in omap1_uart_recalc()
44 return val & clk->enable_bit ? 48000000 : 12000000; in omap1_uart_recalc()
47 unsigned long omap1_sossi_recalc(struct clk *clk) in omap1_sossi_recalc() argument
[all …]
/linux-5.10/arch/arm64/boot/dts/zte/
Dzx296718.dtsi5 * This file is dual-licensed: you can use it either under the terms
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 #include <dt-bindings/input/input.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/gpio/gpio.h>
47 #include <dt-bindings/clock/zx296718-clock.h>
51 #address-cells = <1>;
52 #size-cells = <1>;
53 interrupt-parent = <&gic>;
67 #address-cells = <2>;
[all …]
/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8mq-evk.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 /dts-v1/;
13 compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
16 stdout-path = &uart1;
24 pcie0_refclk: pcie0-refclk {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <100000000>;
30 reg_usdhc2_vmmc: regulator-vsd-3v3 {
[all …]

12345678910>>...21