Lines Matching +full:clk +full:- +full:out +full:- +full:frequency
1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
21 qca,clk-out-frequency:
22 description: Clock output frequency in Hertz.
26 qca,clk-out-strength:
31 qca,keep-pll-enabled:
39 vddio-supply:
44 either connect this to the vddio-regulator (1.5V / 1.8V) or the
45 vddh-regulator (2.5V).
49 vddio-regulator:
55 vddh-regulator:
65 - |
66 #include <dt-bindings/net/qca-ar803x.h>
69 #address-cells = <1>;
70 #size-cells = <0>;
72 phy-mode = "rgmii-id";
74 ethernet-phy@0 {
77 qca,clk-out-frequency = <125000000>;
78 qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
80 vddio-supply = <&vddio>;
82 vddio: vddio-regulator {
83 regulator-min-microvolt = <1800000>;
84 regulator-max-microvolt = <1800000>;
88 - |
89 #include <dt-bindings/net/qca-ar803x.h>
92 #address-cells = <1>;
93 #size-cells = <0>;
95 phy-mode = "rgmii-id";
97 ethernet-phy@0 {
100 qca,clk-out-frequency = <50000000>;
101 qca,keep-pll-enabled;
103 vddio-supply = <&vddh>;
105 vddh: vddh-regulator {