| /linux/Documentation/arch/arm64/ |
| H A D | elf_hwcaps.rst | 19 Userspace software can test for features by acquiring the AT_HWCAP,
32 Where software relies on a feature described by a hwcap, it should check
46 which are described by architected ID registers inaccessible to
53 Functionality implied by idreg.field == val.
58 indicate the absence of functionality implied by other values of
62 described by ID registers alone. These may be described without
70 Functionality implied by ID_AA64PFR0_EL1.FP == 0b0000.
73 Functionality implied by ID_AA64PFR0_EL1.AdvSIMD == 0b0000.
80 Functionality implied by ID_AA64ISAR0_EL1.AES == 0b0001.
83 Functionality implied by ID_AA64ISAR0_EL
[all...] |
| /linux/include/dt-bindings/clock/ |
| H A D | tegra186-clock.h | 376 /** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */
378 /** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */
380 /** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */
384 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
386 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
388 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */
398 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */
400 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */
402 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */
404 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC
[all...] |
| H A D | tegra234-clock.h | 12 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON */
18 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
22 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
24 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
26 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */
28 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */
32 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */
38 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
40 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
42 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC
[all...] |
| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/ |
| H A D | tlb.json | 4 "PublicDescription": "Counts level 1 instruction TLB refills from any Instruction fetch. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB."
8 "PublicDescription": "Counts level 1 data TLB accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event counts for refills caused by preload instructions or hardware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in a translation table walk. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB. This event will not count on an access from an AT(address translation) instruction."
12 "PublicDescription": "Counts level 1 data TLB accesses caused by any memory load or store operation. Note that load or store instructions can be broken up into multiple memory operations. This event does not count TLB maintenance operations."
20 "PublicDescription": "Counts level 2 TLB refills caused by memory operations from both data and instruction fetch, except for those caused by TLB maintenance operations and hardware prefetches."
24 "PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operations."
28 "PublicDescription": "Counts number of demand data translation table walks caused by a miss in the L2 TLB and performing at least one memory access. Translation table walks are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that partial translations that cause a translation table walk are also counted. Also note that this event counts walks triggered by software preloads, but not walks triggered by hardwar
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/snowridgex/ |
| H A D | memory.json | 3 "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",
31 "BriefDescription": "Counts all code reads that were supplied by DRAM.",
37 "PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: 0",
42 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
48 "PublicDescription": "Counts all code reads that were not supplied by the L3 cache. Available PDIST counters: 0",
53 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
59 "PublicDescription": "Counts all code reads that were not supplied by the L3 cache. Available PDIST counters: 0",
64 "BriefDescription": "Counts all code reads that were supplied by DRAM.",
70 "PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: 0",
75 "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by th
[all...] |
| /linux/drivers/staging/media/atomisp/pci/ |
| H A D | ia_css_isp_params.h | 12 /* Code generated by genparam/gencode.c:gen_param_enum() */
64 /* Code generated by genparam/gencode.c:gen_param_offsets() */
137 /* Code generated by genparam/gencode.c:gen_param_process_table() */
146 /* Code generated by genparam/gencode.c:gen_set_function() */
152 /* Code generated by genparam/gencode.c:gen_set_function() */
158 /* Code generated by genparam/gencode.c:gen_set_function() */
164 /* Code generated by genparam/gencode.c:gen_set_function() */
170 /* Code generated by genparam/gencode.c:gen_set_function() */
176 /* Code generated by genparam/gencode.c:gen_set_function() */
182 /* Code generated by genpara
[all...] |
| /linux/drivers/android/ |
| H A D | binder_internal.h | 176 * (protected by @proc->inner_lock)
178 * (protected by @proc->inner_lock)
180 * (protected by binder_dead_nodes_lock)
184 * (protected by @lock)
187 * (protected by @proc->inner_lock if @proc
188 * and by @lock)
190 * (protected by @proc->inner_lock if @proc
191 * and by @lock)
193 * (protected by @proc->inner_lock if @proc
194 * and by
[all...] |
| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| H A D | tlb.json | 4 "PublicDescription": "Counts level 1 instruction TLB refills from any Instruction fetch. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB."
8 "PublicDescription": "Counts level 1 data TLB accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event counts for refills caused by preload instructions or hardware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in a translation table walk. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB. This event will not count on an access from an AT(address translation) instruction."
12 "PublicDescription": "Counts level 1 data TLB accesses caused by any memory load or store operation. Note that load or store instructions can be broken up into multiple memory operations. This event does not count TLB maintenance operations."
20 "PublicDescription": "Counts level 2 TLB refills caused by memory operations from both data and instruction fetch, except for those caused by TLB maintenance operations and hardware prefetches."
24 "PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operations."
28 "PublicDescription": "Counts data memory translation table walks caused by a miss in the L2 TLB driven by a memory access. Note that partial translations that also cause a table walk are counted. This event does not count table walks caused by TL
[all...] |
| /linux/tools/perf/pmu-events/arch/s390/cf_z15/ |
| H A D | crypto6.json | 7 "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU."
14 "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU."
21 "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
28 "PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
35 "PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU."
42 "PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU."
49 "PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by anothe
[all...] |
| /linux/tools/perf/pmu-events/arch/s390/cf_z16/ |
| H A D | crypto6.json | 7 "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU."
14 "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU."
21 "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
28 "PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
35 "PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU."
42 "PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU."
49 "PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by anothe
[all...] |
| /linux/tools/perf/pmu-events/arch/s390/cf_z17/ |
| H A D | crypto6.json | 7 "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU."
14 "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU."
21 "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
28 "PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
35 "PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU."
42 "PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU."
49 "PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by anothe
[all...] |
| /linux/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/ |
| H A D | l2_cache.json | 12 "BriefDescription": "This event counts every write-back of data from the L2 cache caused by L2 replace, non-temporal-store and DC ZVA."
24 "BriefDescription": "This event counts L2D_CACHE caused by read access."
28 "BriefDescription": "This event counts L2D_CACHE caused by write access."
32 "BriefDescription": "This event counts L2D_CACHE_REFILL caused by read access."
36 "BriefDescription": "This event counts L2D_CACHE_REFILL caused by write access."
40 "BriefDescription": "This event counts every write-back of data from the L2 cache caused by L2 replace."
45 "BriefDescription": "This event counts L2D_CACHE caused by demand access."
50 "BriefDescription": "This event counts L2D_CACHE caused by demand read access."
55 "BriefDescription": "This event counts L2D_CACHE caused by demand write access."
60 "BriefDescription": "This event counts L2D_CACHE caused by hardwar
[all...] |
| H A D | l1d_cache.json | 20 "BriefDescription": "This event counts L1D CACHE caused by read access."
24 "BriefDescription": "This event counts L1D CACHE caused by write access."
28 "BriefDescription": "This event counts L1D_CACHE_REFILL caused by read access."
32 "BriefDescription": "This event counts L1D_CACHE_REFILL caused by write access."
37 "BriefDescription": "This event counts L1D_CACHE caused by demand access."
42 "BriefDescription": "This event counts L1D_CACHE caused by demand read access."
47 "BriefDescription": "This event counts L1D_CACHE caused by demand write access."
52 "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand access."
57 "BriefDescription": "This event counts L1D_CACHE_REFILL caused by demand read access."
62 "BriefDescription": "This event counts L1D_CACHE_REFILL caused by deman
[all...] |
| H A D | l3_cache.json | 4 "BriefDescription": "This event counts operations that cause a cache access to the L3 cache, as defined by the sum of L2D_CACHE_REFILL_L3D_CACHE and L2D_CACHE_WB_VICTIM_CLEAN events."
8 "BriefDescription": "This event counts access counted by L3D_CACHE that is a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_CACHE events."
18 "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand access."
23 "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand read access."
28 "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand write access."
33 "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by hardware prefetch or software prefetch."
38 "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by hardware prefetch."
48 "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by demand access."
53 "BriefDescription": "This event counts L2D_CACHE_REFILL_L3D_MISS caused by deman
[all...] |
| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/ |
| H A D | tlb.json | 4 "PublicDescription": "Counts level 1 instruction TLB refills from any Instruction fetch. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB."
8 "PublicDescription": "Counts level 1 data TLB accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event counts for refills caused by preload instructions or hardware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in a translation table walk. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB. This event will not count on an access from an AT(address translation) instruction."
12 "PublicDescription": "Counts level 1 data TLB accesses caused by any memory load or store operation. Note that load or store instructions can be broken up into multiple memory operations. This event does not count TLB maintenance operations."
20 "PublicDescription": "Counts level 2 TLB refills caused by memory operations from both data and instruction fetch, except for those caused by TLB maintenance operations and hardware prefetches."
24 "PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operations."
28 "PublicDescription": "Counts number of demand data translation table walks caused by a miss in the L2 TLB and performing at least one memory access. Translation table walks are counted even if the translation ended up taking a translation fault for reasons different than EPD, E0PD and NFD. Note that partial translations that cause a translation table walk are also counted. Also note that this event counts walks triggered by software preloads, but not walks triggered by hardwar
[all...] |
| /linux/tools/perf/pmu-events/arch/s390/cf_zec12/ |
| H A D | crypto.json | 7 "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU."
14 "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU."
21 "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
28 "PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
35 "PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU."
42 "PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU."
49 "PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by anothe
[all...] |
| /linux/tools/perf/pmu-events/arch/s390/cf_z196/ |
| H A D | crypto.json | 7 "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU."
14 "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU."
21 "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
28 "PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
35 "PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU."
42 "PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU."
49 "PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by anothe
[all...] |
| /linux/tools/perf/pmu-events/arch/s390/cf_z14/ |
| H A D | crypto.json | 7 "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU."
14 "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU."
21 "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
28 "PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
35 "PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU."
42 "PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU."
49 "PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by anothe
[all...] |
| /linux/tools/perf/pmu-events/arch/s390/cf_z13/ |
| H A D | crypto.json | 7 "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU."
14 "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU."
21 "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
28 "PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
35 "PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU."
42 "PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU."
49 "PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by anothe
[all...] |
| /linux/tools/perf/pmu-events/arch/s390/cf_z10/ |
| H A D | crypto.json | 7 "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU."
14 "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU."
21 "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
28 "PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
35 "PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU."
42 "PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU."
49 "PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by anothe
[all...] |
| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/ |
| H A D | mmu.json | 3 "PublicDescription": "Duration of a translation table walk handled by the MMU",
6 "BriefDescription": "Duration of a translation table walk handled by the MMU"
9 "PublicDescription": "Duration of a Stage 1 translation table walk handled by the MMU",
12 "BriefDescription": "Duration of a Stage 1 translation table walk handled by the MMU"
15 "PublicDescription": "Duration of a Stage 2 translation table walk handled by the MMU",
18 "BriefDescription": "Duration of a Stage 2 translation table walk handled by the MMU"
21 "PublicDescription": "Duration of a translation table walk requested by the LSU",
24 "BriefDescription": "Duration of a translation table walk requested by the LSU"
27 "PublicDescription": "Duration of a translation table walk requested by the Instruction Side",
30 "BriefDescription": "Duration of a translation table walk requested by th
[all...] |
| /linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/ |
| H A D | core-imp-def.json | 249 "PublicDescription": "Number of SWOB drains triggered by timeout",
252 "BriefDescription": "Number of SWOB drains triggered by timeout"
255 "PublicDescription": "Number of SWOB drains triggered by system register or special-purpose register read-after-write or specific special-purpose register writes that cause SWOB drain",
258 "BriefDescription": "Number of SWOB drains triggered by system register or special-purpose register read-after-write or specific special-purpose register writes that cause SWOB drain"
261 "PublicDescription": "Number of SWOB drains triggered by system register write when SWOB full",
264 "BriefDescription": "Number of SWOB drains triggered by system register write when SWOB full"
285 "PublicDescription": "Instructions issued by the scheduler",
288 "BriefDescription": "Instructions issued by the scheduler"
309 "PublicDescription": "Uops issued by the scheduler on IXA",
312 "BriefDescription": "Uops issued by th
[all...] |
| /linux/drivers/usb/storage/ |
| H A D | unusual_devs.h | 6 * Current development and maintenance by:
9 * Initial work by:
21 * If you edit this file, please try to keep it sorted first by VendorID,
22 * then by ProductID.
55 /* patch submitted by Vivian Bregier <Vivian.Bregier@imag.fr> */
62 /* Reported by Rodolfo Quesada <rquesada@roqz.net> */
74 /* Reported by Ben Efros <ben@pc-doctor.com> */
82 * Reported by Grant Grundler <grundler@parisc-linux.org>
97 * Reported by Sebastian Kapfer <sebastian_kapfer@gmx.net>
107 /* Patch submitted by Mihne
[all...] |
| /linux/arch/powerpc/xmon/ |
| H A D | ppc.h | 3 Written by Ian Lance Taylor, Cygnus Support
9 License as published by the Free Software Foundation; either version
41 /* The opcode mask. This is used by the disassembler. This is a
44 match (and are presumably filled in by operands). */
59 appear in assembly code, and are terminated by a zero. */
63 /* The table itself is sorted by major opcode number, and is otherwise
82 /* Opcode is supported by the Motorola PowerPC 601 processor. The 601
104 /* Opcode is supported by Altivec Vector Unit */
107 /* Opcode is supported by PowerPC 403 processor. */
110 /* Opcode is supported by PowerP
[all...] |
| /linux/drivers/infiniband/sw/rxe/ |
| H A D | rxe_queue.h | 24 * by user so a local copy is used and a shared copy is
26 * - By passing the type in the parameter list separate from q
37 * @QUEUE_TYPE_TO_CLIENT: Queue is written by rxe driver and
38 * read by client which may be a user space
40 * Used by rxe internals only.
41 * @QUEUE_TYPE_FROM_CLIENT: Queue is written by client and
42 * read by rxe driver.
43 * Used by rxe internals only.
44 * @QUEUE_TYPE_FROM_ULP: Queue is written by kernel ulp and
45 * read by rx
[all...] |