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/linux/drivers/net/ipa/reg/
H A Dipa_reg-v3.1.c6 #include <linux/bits.h>
18 /* Bits 5-31 reserved */
41 /* Bits 17-31 reserved */
52 /* Bits 22-23 reserved */
54 /* Bits 25-31 reserved */
69 /* Bits 8-31 reserved */
83 /* Bits 1-3 reserved */
85 /* Bits 5-7 reserved */
87 /* Bits 9-11 reserved */
89 /* Bits 13-31 reserved */
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Duconn.c34 nvkm_uconn_uevent_gsp(struct nvkm_object *object, u64 token, u32 bits) in nvkm_uconn_uevent_gsp() argument
40 if (bits & NVKM_DPYID_PLUG) in nvkm_uconn_uevent_gsp()
42 if (bits & NVKM_DPYID_UNPLUG) in nvkm_uconn_uevent_gsp()
44 if (bits & NVKM_DPYID_IRQ) in nvkm_uconn_uevent_gsp()
51 nvkm_uconn_uevent_aux(struct nvkm_object *object, u64 token, u32 bits) in nvkm_uconn_uevent_aux() argument
57 if (bits & NVKM_I2C_PLUG) in nvkm_uconn_uevent_aux()
59 if (bits & NVKM_I2C_UNPLUG) in nvkm_uconn_uevent_aux()
61 if (bits & NVKM_I2C_IRQ) in nvkm_uconn_uevent_aux()
68 nvkm_uconn_uevent_gpio(struct nvkm_object *object, u64 token, u32 bits) in nvkm_uconn_uevent_gpio() argument
74 if (bits & NVKM_GPIO_HI) in nvkm_uconn_uevent_gpio()
[all …]
/linux/fs/ocfs2/cluster/
H A Dmasklog.h16 * maintained with help from /proc. If any of the bits match the message is
24 * one of the longs. This leads to having infrequently given bits that are
25 * frequently matched in the high bits.
37 * indication of which bits are allowed (allow) or denied (off/deny).
51 * Echoing allow/deny/off string into the logmask files can flip the bits
59 * The debugfs.ocfs2 tool can also flip the bits with the -l option:
67 /* bits that are frequently given and infrequently matched in the low word */
87 /* bits that are infrequently given and frequently matched in the high word */
118 #define __mlog_test_u64(mask, bits) \ argument
119 ( (u32)(mask & 0xffffffff) & bits.words[0] || \
[all …]
/linux/drivers/clk/at91/
H A Dsckc.c34 const struct clk_slow_bits *bits; member
43 const struct clk_slow_bits *bits; member
53 const struct clk_slow_bits *bits; member
64 const struct clk_slow_bits *bits; member
76 if (tmp & (osc->bits->cr_osc32byp | osc->bits->cr_osc32en)) in clk_slow_osc_prepare()
79 writel(tmp | osc->bits->cr_osc32en, sckcr); in clk_slow_osc_prepare()
95 if (tmp & osc->bits->cr_osc32byp) in clk_slow_osc_unprepare()
98 writel(tmp & ~osc->bits->cr_osc32en, sckcr); in clk_slow_osc_unprepare()
107 if (tmp & osc->bits->cr_osc32byp) in clk_slow_osc_is_prepared()
110 return !!(tmp & osc->bits->cr_osc32en); in clk_slow_osc_is_prepared()
[all …]
/linux/drivers/video/fbdev/core/
H A Dfb_draw.h21 /* move the address pointer forward with the number of bits */
24 unsigned int bits = (unsigned int)adr->bits + offset; in fb_address_forward() local
26 adr->bits = bits & (BITS_PER_LONG - 1u); in fb_address_forward()
27 adr->address += (bits & ~(BITS_PER_LONG - 1u)) / BITS_PER_BYTE; in fb_address_forward()
30 /* move the address pointer backwards with the number of bits */
33 int bits = adr->bits - (int)offset; in fb_address_backward() local
35 adr->bits = bits & (BITS_PER_LONG - 1); in fb_address_backward()
36 if (bits < 0) in fb_address_backward()
37 adr->address -= (adr->bits - bits) / BITS_PER_BYTE; in fb_address_backward()
39 adr->address += (bits - adr->bits) / BITS_PER_BYTE; in fb_address_backward()
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-apq8084.dtsi256 bits = <0 8>;
261 bits = <0 6>;
266 bits = <6 6>;
271 bits = <4 6>;
276 bits = <2 6>;
281 bits = <0 6>;
286 bits = <6 6>;
291 bits = <4 6>;
296 bits = <2 6>;
301 bits = <0 6>;
[all …]
/linux/include/drm/display/
H A Ddrm_dsc.h61 * Bits/group offset to apply to target for this group
75 * Bits per component for previous reconstructed line buffer
79 * @bits_per_component: Bits per component to code (8/10/12)
114 * Offset to bits/group used by RC to determine QP adjustment
119 * Offset to bits/group used by RC to determine QP adjustment
124 * Target bits per pixel with 4 fractional bits, bits_per_pixel << 4
129 * Factor to determine if an edge is present based on the bits produced
162 * Number of additional bits allocated for each group on the first
225 * @mux_word_size: Mux word size (in bits) for SSM mode
235 * @rc_bits: Rate control buffer size in bits
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3566.dtsi11 opp-hz = /bits/ 64 <408000000>;
17 opp-hz = /bits/ 64 <600000000>;
23 opp-hz = /bits/ 64 <816000000>;
30 opp-hz = /bits/ 64 <1104000000>;
36 opp-hz = /bits/ 64 <1416000000>;
42 opp-hz = /bits/ 64 <1608000000>;
48 opp-hz = /bits/ 64 <1800000000>;
58 opp-hz = /bits/ 64 <200000000>;
63 opp-hz = /bits/ 64 <300000000>;
68 opp-hz = /bits/ 64 <400000000>;
[all …]
/linux/drivers/media/rc/
H A Dir-imon-decoder.c19 * This protocol has 30 bits. The format is one IMON_UNIT header pulse,
20 * followed by 30 bits. Each bit is one IMON_UNIT check field, and then
22 * The check field is always space for some bits, for others it is pulse if
24 * defines which bits are of type check.
27 * the lower bits are all set, iow. the last pulse is for the lowest
43 if (imon->bits == 0x299115b7) in ir_imon_decode_scancode()
46 if ((imon->bits & 0xfc0000ff) == 0x680000b7) { in ir_imon_decode_scancode()
50 buf = imon->bits >> 16; in ir_imon_decode_scancode()
53 if (imon->bits & 0x02000000) in ir_imon_decode_scancode()
55 buf = imon->bits >> 8; in ir_imon_decode_scancode()
[all …]
/linux/sound/soc/ti/
H A Ddavinci-mcasp.h101 * Register Bits
107 * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
108 * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
122 * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
129 * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
140 * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
151 * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
159 * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
167 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
176 * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
[all …]
/linux/drivers/gpu/drm/gma500/
H A Doaktrail.h77 u16 Panel_Backlight_Inverter_Descriptor;/* 16 bits, as follows */
78 /* Bit 0, Frequency, 15 bits,0 - 32767Hz */
81 /*16 bits, Defined as follows: */
83 /* Bit 0, Type, 2 bits, */
88 /* Bit 2, Pixel Format, 4 bits */
93 /* Bit 6, Reserved, 2 bits, 00b */
94 /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
95 /* Bit 14, Reserved, 2 bits, 00b */
106 u16 Panel_Backlight_Inverter_Descriptor;/*16 bits, as follows*/
107 /*Bit 0, Frequency, 16 bits, 0 - 32767Hz*/
[all …]
/linux/arch/mips/lantiq/falcon/
H A Dsysctrl.c82 & clk->bits) != test)); in sysctl_wait()
85 clk->module, clk->bits, test, in sysctl_wait()
86 sysctl_r32(clk->module, reg) & clk->bits); in sysctl_wait()
91 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN); in sysctl_activate()
92 sysctl_w32(clk->module, clk->bits, SYSCTL_ACT); in sysctl_activate()
93 sysctl_wait(clk, clk->bits, SYSCTL_ACTS); in sysctl_activate()
99 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR); in sysctl_deactivate()
100 sysctl_w32(clk->module, clk->bits, SYSCTL_DEACT); in sysctl_deactivate()
106 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN); in sysctl_clken()
107 sysctl_w32(clk->module, clk->bits, SYSCTL_ACT); in sysctl_clken()
[all …]
/linux/include/trace/events/
H A Dfsi_master_gpio.h12 TP_PROTO(const struct fsi_master_gpio *master, int bits, uint64_t msg),
13 TP_ARGS(master, bits, msg),
16 __field(int, bits)
21 __entry->bits = bits;
22 __entry->msg = msg & ((1ull<<bits) - 1);
26 (__entry->bits + 3) / 4,
28 __entry->bits
33 TP_PROTO(const struct fsi_master_gpio *master, int bits, uint64_t msg),
34 TP_ARGS(master, bits, msg),
37 __field(int, bits)
[all …]
/linux/Documentation/devicetree/bindings/interconnect/
H A Dmediatek,cci.yaml84 opp-hz = /bits/ 64 <273000000>;
88 opp-hz = /bits/ 64 <338000000>;
92 opp-hz = /bits/ 64 <403000000>;
96 opp-hz = /bits/ 64 <463000000>;
100 opp-hz = /bits/ 64 <546000000>;
104 opp-hz = /bits/ 64 <624000000>;
108 opp-hz = /bits/ 64 <689000000>;
112 opp-hz = /bits/ 64 <767000000>;
116 opp-hz = /bits/ 64 <845000000>;
120 opp-hz = /bits/ 64 <871000000>;
[all …]
/linux/drivers/net/ethernet/brocade/bna/
H A Dbna_hw_defs.h32 #define BFI_VLAN_WORD_SHIFT 5 /* 32 bits */
34 #define BFI_VLAN_BLOCK_SHIFT 9 /* 512 bits */
88 (_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0 | \
90 (_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0 | \
92 (_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK); \
93 (_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK); \
94 (_bna)->bits.halt_status_bits = __HFN_INT_LL_HALT; \
95 (_bna)->bits.halt_mask_bits = __HFN_INT_LL_HALT; \
108 (_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0_CT2 | \
110 (_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0_CT2 | \
[all …]
/linux/tools/perf/util/
H A Dpmu.y29 static void perf_pmu__set_format(unsigned long *bits, long from, long to) in perf_pmu__set_format() argument
36 memset(bits, 0, BITS_TO_BYTES(PERF_PMU_FORMAT_BITS)); in perf_pmu__set_format()
38 __set_bit(b, bits); in perf_pmu__set_format()
46 %type <bits> bit_term
47 %type <bits> bits
52 DECLARE_BITMAP(bits, PERF_PMU_FORMAT_BITS);
63 PP_CONFIG ':' bits
68 PP_CONFIG PP_VALUE ':' bits
73 bits:
74 bits ',' bit_term
/linux/arch/arm64/kvm/
H A Dtrng.c26 DECLARE_BITMAP(bits, TRNG_MAX_BITS64); in kvm_trng_do_rnd()
35 /* get as many bits as we need to fulfil the request */ in kvm_trng_do_rnd()
37 bits[i] = get_random_long(); in kvm_trng_do_rnd()
39 bitmap_clear(bits, num_bits, TRNG_MAX_BITS64 - num_bits); in kvm_trng_do_rnd()
42 smccc_set_retval(vcpu, TRNG_SUCCESS, lower_32_bits(bits[1]), in kvm_trng_do_rnd()
43 upper_32_bits(bits[0]), lower_32_bits(bits[0])); in kvm_trng_do_rnd()
45 smccc_set_retval(vcpu, TRNG_SUCCESS, bits[2], bits[1], bits[0]); in kvm_trng_do_rnd()
47 memzero_explicit(bits, sizeof(bits)); in kvm_trng_do_rnd()
/linux/drivers/gpu/drm/tegra/
H A Dhda.c14 unsigned int mul, div, bits, channels; in tegra_hda_parse_format() local
33 fmt->bits = 8; in tegra_hda_parse_format()
37 fmt->bits = 16; in tegra_hda_parse_format()
41 fmt->bits = 20; in tegra_hda_parse_format()
45 fmt->bits = 24; in tegra_hda_parse_format()
49 fmt->bits = 32; in tegra_hda_parse_format()
53 bits = (format & AC_FMT_BITS_MASK) >> AC_FMT_BITS_SHIFT; in tegra_hda_parse_format()
54 WARN(1, "invalid number of bits: %#x\n", bits); in tegra_hda_parse_format()
55 fmt->bits = 8; in tegra_hda_parse_format()
/linux/drivers/pmdomain/imx/
H A Dgpcv2.c293 } bits; member
350 if (domain->bits.pxx) { in imx_pgc_power_up()
353 domain->bits.pxx, domain->bits.pxx); in imx_pgc_power_up()
360 !(reg_val & domain->bits.pxx), in imx_pgc_power_up()
380 if (domain->bits.hskreq) { in imx_pgc_power_up()
382 domain->bits.hskreq, domain->bits.hskreq); in imx_pgc_power_up()
386 * (reg_val & domain->bits.hskack), 0, in imx_pgc_power_up()
442 if (domain->bits.hskreq) { in imx_pgc_power_down()
444 domain->bits.hskreq); in imx_pgc_power_down()
448 !(reg_val & domain->bits.hskack), in imx_pgc_power_down()
[all …]
/linux/drivers/staging/media/atomisp/pci/
H A Dia_css_frac.h17 * NOTE: the 16 bit fixed point types actually occupy 32 bits
20 /* Unsigned fixed point value, 0 integer bits, 16 fractional bits */
22 /* Unsigned fixed point value, 5 integer bits, 11 fractional bits */
24 /* Unsigned fixed point value, 8 integer bits, 8 fractional bits */
26 /* Signed fixed point value, 0 integer bits, 15 fractional bits */
/linux/include/linux/can/
H A Dlength.h10 #include <linux/bits.h>
16 * Size of a Classical CAN Standard Frame header in bits
18 * Name of Field Bits
34 * Size of a Classical CAN Extended Frame header in bits
36 * Name of Field Bits
55 * Size of a CAN-FD Standard Frame in bits
57 * Name of Field Bits
76 * Size of a CAN-FD Extended Frame in bits
78 * Name of Field Bits
99 * Size of a CAN CRC Field in bits
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dpixfmt-packed-yuv.rst16 - 'Y', 'Cb' and 'Cr' denote bits of the luma, blue chroma (also known as
18 denotes bits of the alpha component (if supported by the format), and 'X'
19 denotes padding bits.
28 The next table lists the packed YUV 4:4:4 formats with less than 8 bits per
31 order, and on the number of bits for each component. For instance the YUV565
150 For the YUV444 and YUV555 formats, the value of alpha bits is undefined
156 The next table lists the packed YUV 4:4:4 formats with 8 bits per component.
158 memory, and on the total number of bits per pixel. For instance, the VUYX32
257 - The padding bits contain undefined values that must be ignored by all
260 The next table lists the packed YUV 4:4:4 formats with 12 bits per component.
[all …]
/linux/lib/crc/
H A Dcrc4.c19 * @bits: number of bits in @x to checksum
23 * The @x value is treated as left-aligned, and bits above @bits are ignored
26 uint8_t crc4(uint8_t c, uint64_t x, int bits) in crc4() argument
31 x &= (1ull << bits) - 1; in crc4()
33 /* Align to 4-bits */ in crc4()
34 bits = (bits + 3) & ~0x3; in crc4()
37 for (i = bits - 4; i >= 0; i -= 4) in crc4()
/linux/Documentation/devicetree/bindings/input/touchscreen/
H A Dadi,ad7879.yaml49 This property has to be a '/bits/ 8' value
60 This property has to be a '/bits/ 8' value
71 This property has to be a '/bits/ 8' value
82 This property has to be a '/bits/ 8' value
90 This property has to be a '/bits/ 8' value
120 adi,first-conversion-delay = /bits/ 8 <3>;
121 adi,acquisition-time = /bits/ 8 <1>;
122 adi,median-filter-size = /bits/ 8 <2>;
123 adi,averaging = /bits/ 8 <1>;
124 adi,conversion-interval = /bits/ 8 <255>;
[all …]
/linux/drivers/mfd/
H A Ddb8500-prcmu-regs.h15 #define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end)) macro
120 #define PRCM_PLL_FREQ_D_MASK BITS(0, 7)
122 #define PRCM_PLL_FREQ_N_MASK BITS(8, 13)
124 #define PRCM_PLL_FREQ_R_MASK BITS(16, 18)
143 #define PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK BITS(0, 2)
145 #define PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK BITS(8, 10)
153 #define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK BITS(0, 7)
155 #define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK BITS(8, 15)
157 #define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK BITS(16, 23)
166 #define PRCM_CLKOCR_CLKOUT0_MASK BITS(0, 13)
[all …]

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