xref: /linux/arch/arm64/boot/dts/rockchip/rk3566.dtsi (revision c771600c6af14749609b49565ffb4cac2959710d)
1016c0e8aSPeter Geis// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2016c0e8aSPeter Geis
3*853f9632SDragan Simic#include "rk3566-base.dtsi"
4016c0e8aSPeter Geis
5016c0e8aSPeter Geis/ {
6*853f9632SDragan Simic	cpu0_opp_table: opp-table-0 {
7*853f9632SDragan Simic		compatible = "operating-points-v2";
8*853f9632SDragan Simic		opp-shared;
9*853f9632SDragan Simic
10*853f9632SDragan Simic		opp-408000000 {
11*853f9632SDragan Simic			opp-hz = /bits/ 64 <408000000>;
12*853f9632SDragan Simic			opp-microvolt = <850000 850000 1150000>;
13*853f9632SDragan Simic			clock-latency-ns = <40000>;
14016c0e8aSPeter Geis		};
15016c0e8aSPeter Geis
16*853f9632SDragan Simic		opp-600000000 {
17*853f9632SDragan Simic			opp-hz = /bits/ 64 <600000000>;
18*853f9632SDragan Simic			opp-microvolt = <850000 850000 1150000>;
19*853f9632SDragan Simic			clock-latency-ns = <40000>;
209f4c480fSPeter Geis		};
219f4c480fSPeter Geis
22*853f9632SDragan Simic		opp-816000000 {
23*853f9632SDragan Simic			opp-hz = /bits/ 64 <816000000>;
24*853f9632SDragan Simic			opp-microvolt = <850000 850000 1150000>;
25*853f9632SDragan Simic			clock-latency-ns = <40000>;
26*853f9632SDragan Simic			opp-suspend;
27*853f9632SDragan Simic		};
28*853f9632SDragan Simic
29*853f9632SDragan Simic		opp-1104000000 {
30*853f9632SDragan Simic			opp-hz = /bits/ 64 <1104000000>;
31*853f9632SDragan Simic			opp-microvolt = <900000 900000 1150000>;
32*853f9632SDragan Simic			clock-latency-ns = <40000>;
33*853f9632SDragan Simic		};
34*853f9632SDragan Simic
35*853f9632SDragan Simic		opp-1416000000 {
36*853f9632SDragan Simic			opp-hz = /bits/ 64 <1416000000>;
37*853f9632SDragan Simic			opp-microvolt = <1025000 1025000 1150000>;
38*853f9632SDragan Simic			clock-latency-ns = <40000>;
39*853f9632SDragan Simic		};
40*853f9632SDragan Simic
41*853f9632SDragan Simic		opp-1608000000 {
42*853f9632SDragan Simic			opp-hz = /bits/ 64 <1608000000>;
43*853f9632SDragan Simic			opp-microvolt = <1100000 1100000 1150000>;
44*853f9632SDragan Simic			clock-latency-ns = <40000>;
45*853f9632SDragan Simic		};
46*853f9632SDragan Simic
47*853f9632SDragan Simic		opp-1800000000 {
48*853f9632SDragan Simic			opp-hz = /bits/ 64 <1800000000>;
49*853f9632SDragan Simic			opp-microvolt = <1150000 1150000 1150000>;
50*853f9632SDragan Simic			clock-latency-ns = <40000>;
51016c0e8aSPeter Geis		};
52016c0e8aSPeter Geis	};
539f4c480fSPeter Geis
54*853f9632SDragan Simic	gpu_opp_table: opp-table-1 {
55*853f9632SDragan Simic		compatible = "operating-points-v2";
56*853f9632SDragan Simic
57*853f9632SDragan Simic		opp-200000000 {
58*853f9632SDragan Simic			opp-hz = /bits/ 64 <200000000>;
59*853f9632SDragan Simic			opp-microvolt = <850000 850000 1000000>;
609f4c480fSPeter Geis		};
619d6c6d97SSascha Hauer
62*853f9632SDragan Simic		opp-300000000 {
63*853f9632SDragan Simic			opp-hz = /bits/ 64 <300000000>;
64*853f9632SDragan Simic			opp-microvolt = <850000 850000 1000000>;
65*853f9632SDragan Simic		};
66*853f9632SDragan Simic
67*853f9632SDragan Simic		opp-400000000 {
68*853f9632SDragan Simic			opp-hz = /bits/ 64 <400000000>;
69*853f9632SDragan Simic			opp-microvolt = <850000 850000 1000000>;
70*853f9632SDragan Simic		};
71*853f9632SDragan Simic
72*853f9632SDragan Simic		opp-600000000 {
73*853f9632SDragan Simic			opp-hz = /bits/ 64 <600000000>;
74*853f9632SDragan Simic			opp-microvolt = <900000 900000 1000000>;
75*853f9632SDragan Simic		};
76*853f9632SDragan Simic
77*853f9632SDragan Simic		opp-700000000 {
78*853f9632SDragan Simic			opp-hz = /bits/ 64 <700000000>;
79*853f9632SDragan Simic			opp-microvolt = <950000 950000 1000000>;
80*853f9632SDragan Simic		};
81*853f9632SDragan Simic
82*853f9632SDragan Simic		opp-800000000 {
83*853f9632SDragan Simic			opp-hz = /bits/ 64 <800000000>;
84*853f9632SDragan Simic			opp-microvolt = <1000000 1000000 1000000>;
85*853f9632SDragan Simic		};
86*853f9632SDragan Simic	};
87*853f9632SDragan Simic};
88*853f9632SDragan Simic
89*853f9632SDragan Simic&cpu0 {
90*853f9632SDragan Simic	operating-points-v2 = <&cpu0_opp_table>;
91*853f9632SDragan Simic};
92*853f9632SDragan Simic
93*853f9632SDragan Simic&cpu1 {
94*853f9632SDragan Simic	operating-points-v2 = <&cpu0_opp_table>;
95*853f9632SDragan Simic};
96*853f9632SDragan Simic
97*853f9632SDragan Simic&cpu2 {
98*853f9632SDragan Simic	operating-points-v2 = <&cpu0_opp_table>;
99*853f9632SDragan Simic};
100*853f9632SDragan Simic
101*853f9632SDragan Simic&cpu3 {
102*853f9632SDragan Simic	operating-points-v2 = <&cpu0_opp_table>;
103*853f9632SDragan Simic};
104*853f9632SDragan Simic
105*853f9632SDragan Simic&gpu {
106*853f9632SDragan Simic	operating-points-v2 = <&gpu_opp_table>;
1079d6c6d97SSascha Hauer};
108