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/linux/drivers/gpio/
H A Dgpio-omap.c78 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
84 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) argument
109 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, in omap_set_gpio_direction() argument
112 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, in omap_set_gpio_direction()
118 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, in omap_set_gpio_dataout_reg() argument
121 void __iomem *reg = bank in omap_set_gpio_dataout_reg()
136 omap_set_gpio_dataout_mask(struct gpio_bank * bank,unsigned offset,int enable) omap_set_gpio_dataout_mask() argument
143 omap_gpio_dbck_enable(struct gpio_bank * bank) omap_gpio_dbck_enable() argument
154 omap_gpio_dbck_disable(struct gpio_bank * bank) omap_gpio_dbck_disable() argument
181 omap2_set_gpio_debounce(struct gpio_bank * bank,unsigned offset,unsigned debounce) omap2_set_gpio_debounce() argument
233 omap_clear_gpio_debounce(struct gpio_bank * bank,unsigned offset) omap_clear_gpio_debounce() argument
263 omap_gpio_is_off_wakeup_capable(struct gpio_bank * bank,u32 gpio_mask) omap_gpio_is_off_wakeup_capable() argument
273 omap_set_gpio_trigger(struct gpio_bank * bank,int gpio,unsigned trigger) omap_set_gpio_trigger() argument
325 omap_toggle_gpio_edge_triggering(struct gpio_bank * bank,int gpio) omap_toggle_gpio_edge_triggering() argument
334 omap_set_gpio_triggering(struct gpio_bank * bank,int gpio,unsigned trigger) omap_set_gpio_triggering() argument
374 omap_enable_gpio_module(struct gpio_bank * bank,unsigned offset) omap_enable_gpio_module() argument
395 omap_disable_gpio_module(struct gpio_bank * bank,unsigned offset) omap_disable_gpio_module() argument
409 omap_gpio_is_input(struct gpio_bank * bank,unsigned offset) omap_gpio_is_input() argument
416 omap_gpio_init_irq(struct gpio_bank * bank,unsigned offset) omap_gpio_init_irq() argument
427 struct gpio_bank *bank = omap_irq_data_get_bank(d); omap_gpio_irq_type() local
470 omap_clear_gpio_irqbank(struct gpio_bank * bank,int gpio_mask) omap_clear_gpio_irqbank() argument
487 omap_clear_gpio_irqstatus(struct gpio_bank * bank,unsigned offset) omap_clear_gpio_irqstatus() argument
493 omap_get_gpio_irqbank_mask(struct gpio_bank * bank) omap_get_gpio_irqbank_mask() argument
507 omap_set_gpio_irqenable(struct gpio_bank * bank,unsigned offset,int enable) omap_set_gpio_irqenable() argument
545 struct gpio_bank *bank = omap_irq_data_get_bank(d); omap_gpio_wake_enable() local
564 struct gpio_bank *bank = gpiobank; omap_gpio_irq_handler() local
627 struct gpio_bank *bank = omap_irq_data_get_bank(d); omap_gpio_irq_startup() local
646 struct gpio_bank *bank = omap_irq_data_get_bank(d); omap_gpio_irq_shutdown() local
663 struct gpio_bank *bank = omap_irq_data_get_bank(data); omap_gpio_irq_bus_lock() local
670 struct gpio_bank *bank = omap_irq_data_get_bank(data); gpio_irq_bus_sync_unlock() local
677 struct gpio_bank *bank = omap_irq_data_get_bank(d); omap_gpio_mask_irq() local
690 struct gpio_bank *bank = omap_irq_data_get_bank(d); omap_gpio_unmask_irq() local
716 struct gpio_bank *bank = omap_irq_data_get_bank(d); omap_gpio_irq_print_chip() local
752 struct gpio_bank *bank = dev_get_drvdata(dev); omap_mpuio_suspend_noirq() local
766 struct gpio_bank *bank = dev_get_drvdata(dev); omap_mpuio_resume_noirq() local
800 omap_mpuio_init(struct gpio_bank * bank) omap_mpuio_init() argument
812 struct gpio_bank *bank = gpiochip_get_data(chip); omap_gpio_request() local
827 struct gpio_bank *bank = gpiochip_get_data(chip); omap_gpio_free() local
844 struct gpio_bank *bank = gpiochip_get_data(chip); omap_gpio_get_direction() local
854 struct gpio_bank *bank; omap_gpio_input() local
866 struct gpio_bank *bank = gpiochip_get_data(chip); omap_gpio_get() local
879 struct gpio_bank *bank; omap_gpio_output() local
893 struct gpio_bank *bank = gpiochip_get_data(chip); omap_gpio_get_multiple() local
915 struct gpio_bank *bank; omap_gpio_debounce() local
958 struct gpio_bank *bank; omap_gpio_set() local
972 struct gpio_bank *bank = gpiochip_get_data(chip); omap_gpio_set_multiple() local
988 omap_gpio_show_rev(struct gpio_bank * bank) omap_gpio_show_rev() argument
1003 omap_gpio_mod_init(struct gpio_bank * bank) omap_gpio_mod_init() argument
1030 omap_gpio_chip_init(struct gpio_bank * bank,struct device * pm_dev) omap_gpio_chip_init() argument
1113 omap_gpio_restore_context(struct gpio_bank * bank) omap_gpio_restore_context() argument
1138 omap_gpio_idle(struct gpio_bank * bank,bool may_lose_context) omap_gpio_idle() argument
1185 omap_gpio_unidle(struct gpio_bank * bank) omap_gpio_unidle() argument
1279 struct gpio_bank *bank; gpio_omap_cpu_notifier() local
1402 struct gpio_bank *bank; omap_gpio_probe() local
1497 struct gpio_bank *bank = platform_get_drvdata(pdev); omap_gpio_remove() local
1508 struct gpio_bank *bank = dev_get_drvdata(dev); omap_gpio_runtime_suspend() local
1521 struct gpio_bank *bank = dev_get_drvdata(dev); omap_gpio_runtime_resume() local
1534 struct gpio_bank *bank = dev_get_drvdata(dev); omap_gpio_suspend() local
1546 struct gpio_bank *bank = dev_get_drvdata(dev); omap_gpio_resume() local
[all...]
H A Dgpio-rockchip.c83 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, in rockchip_gpio_writel() argument
86 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel()
88 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_writel()
94 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank, in rockchip_gpio_readl() argument
97 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_readl()
100 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_readl()
108 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_writel_bit() argument
112 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel_bit()
115 if (bank->gpio_type == GPIO_TYPE_V2) { in rockchip_gpio_writel_bit()
130 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_readl_bit() argument
150 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); rockchip_gpio_get_direction() local
163 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); rockchip_gpio_set_direction() local
183 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); rockchip_gpio_set() local
195 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); rockchip_gpio_get() local
209 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); rockchip_gpio_set_debounce() local
316 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); rockchip_gpio_to_irq() local
343 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); rockchip_irq_demux() local
395 struct rockchip_pin_bank *bank = gc->private; rockchip_irq_set_type() local
480 struct rockchip_pin_bank *bank = gc->private; rockchip_irq_reqres() local
488 struct rockchip_pin_bank *bank = gc->private; rockchip_irq_relres() local
496 struct rockchip_pin_bank *bank = gc->private; rockchip_irq_suspend() local
505 struct rockchip_pin_bank *bank = gc->private; rockchip_irq_resume() local
520 rockchip_interrupts_register(struct rockchip_pin_bank * bank) rockchip_interrupts_register() argument
584 rockchip_gpiolib_register(struct rockchip_pin_bank * bank) rockchip_gpiolib_register() argument
648 rockchip_get_bank_data(struct rockchip_pin_bank * bank) rockchip_get_bank_data() argument
702 struct rockchip_pin_bank *bank; rockchip_gpio_find_bank() local
723 struct rockchip_pin_bank *bank = NULL; rockchip_gpio_probe() local
800 struct rockchip_pin_bank *bank = platform_get_drvdata(pdev); rockchip_gpio_remove() local
[all...]
H A Dgpio-brcmstb.c27 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32))) argument
28 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN) argument
29 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA) argument
30 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR) argument
31 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_E argument
32 GIO_EI(bank) global() argument
33 GIO_MASK(bank) global() argument
34 GIO_LEVEL(bank) global() argument
35 GIO_STAT(bank) global() argument
66 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); brcmstb_gpio_gc_to_priv() local
71 __brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank * bank) __brcmstb_gpio_get_active_irqs() argument
80 brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank * bank) brcmstb_gpio_get_active_irqs() argument
93 brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq,struct brcmstb_gpio_bank * bank) brcmstb_gpio_hwirq_to_offset() argument
98 brcmstb_gpio_set_imask(struct brcmstb_gpio_bank * bank,unsigned int hwirq,bool enable) brcmstb_gpio_set_imask() argument
133 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); brcmstb_gpio_irq_mask() local
141 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); brcmstb_gpio_irq_unmask() local
149 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); brcmstb_gpio_irq_ack() local
159 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); brcmstb_gpio_irq_set_type() local
235 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); brcmstb_gpio_irq_set_wake() local
262 brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank * bank) brcmstb_gpio_irq_bank_handler() argument
287 struct brcmstb_gpio_bank *bank; brcmstb_gpio_irq_handler() local
301 struct brcmstb_gpio_bank *bank; brcmstb_gpio_hwirq_to_bank() local
325 struct brcmstb_gpio_bank *bank = brcmstb_gpio_irq_map() local
377 struct brcmstb_gpio_bank *bank; brcmstb_gpio_remove() local
404 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); brcmstb_gpio_of_xlate() local
494 brcmstb_gpio_bank_save(struct brcmstb_gpio_priv * priv,struct brcmstb_gpio_bank * bank) brcmstb_gpio_bank_save() argument
507 struct brcmstb_gpio_bank *bank; brcmstb_gpio_quiesce() local
539 brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv * priv,struct brcmstb_gpio_bank * bank) brcmstb_gpio_bank_restore() argument
558 struct brcmstb_gpio_bank *bank; brcmstb_gpio_resume() local
637 struct brcmstb_gpio_bank *bank; brcmstb_gpio_probe() local
[all...]
/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_gen4_hw_csr_data.c11 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument
13 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
16 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_head() argument
19 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
22 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument
24 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
27 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_tail() argument
30 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
33 static u32 read_csr_stat(void __iomem *csr_base_addr, u32 bank) in read_csr_stat() argument
35 return READ_CSR_STAT(csr_base_addr, bank); in read_csr_stat()
38 read_csr_uo_stat(void __iomem * csr_base_addr,u32 bank) read_csr_uo_stat() argument
43 read_csr_e_stat(void __iomem * csr_base_addr,u32 bank) read_csr_e_stat() argument
48 read_csr_ne_stat(void __iomem * csr_base_addr,u32 bank) read_csr_ne_stat() argument
53 read_csr_nf_stat(void __iomem * csr_base_addr,u32 bank) read_csr_nf_stat() argument
58 read_csr_f_stat(void __iomem * csr_base_addr,u32 bank) read_csr_f_stat() argument
63 read_csr_c_stat(void __iomem * csr_base_addr,u32 bank) read_csr_c_stat() argument
68 read_csr_exp_stat(void __iomem * csr_base_addr,u32 bank) read_csr_exp_stat() argument
73 read_csr_exp_int_en(void __iomem * csr_base_addr,u32 bank) read_csr_exp_int_en() argument
78 write_csr_exp_int_en(void __iomem * csr_base_addr,u32 bank,u32 value) write_csr_exp_int_en() argument
84 read_csr_ring_config(void __iomem * csr_base_addr,u32 bank,u32 ring) read_csr_ring_config() argument
90 write_csr_ring_config(void __iomem * csr_base_addr,u32 bank,u32 ring,u32 value) write_csr_ring_config() argument
96 read_csr_ring_base(void __iomem * csr_base_addr,u32 bank,u32 ring) read_csr_ring_base() argument
102 write_csr_ring_base(void __iomem * csr_base_addr,u32 bank,u32 ring,dma_addr_t addr) write_csr_ring_base() argument
108 read_csr_int_en(void __iomem * csr_base_addr,u32 bank) read_csr_int_en() argument
113 write_csr_int_en(void __iomem * csr_base_addr,u32 bank,u32 value) write_csr_int_en() argument
118 read_csr_int_flag(void __iomem * csr_base_addr,u32 bank) read_csr_int_flag() argument
123 write_csr_int_flag(void __iomem * csr_base_addr,u32 bank,u32 value) write_csr_int_flag() argument
129 read_csr_int_srcsel(void __iomem * csr_base_addr,u32 bank) read_csr_int_srcsel() argument
134 write_csr_int_srcsel(void __iomem * csr_base_addr,u32 bank) write_csr_int_srcsel() argument
139 write_csr_int_srcsel_w_val(void __iomem * csr_base_addr,u32 bank,u32 value) write_csr_int_srcsel_w_val() argument
145 read_csr_int_col_en(void __iomem * csr_base_addr,u32 bank) read_csr_int_col_en() argument
150 write_csr_int_col_en(void __iomem * csr_base_addr,u32 bank,u32 value) write_csr_int_col_en() argument
155 read_csr_int_col_ctl(void __iomem * csr_base_addr,u32 bank) read_csr_int_col_ctl() argument
160 write_csr_int_col_ctl(void __iomem * csr_base_addr,u32 bank,u32 value) write_csr_int_col_ctl() argument
166 read_csr_int_flag_and_col(void __iomem * csr_base_addr,u32 bank) read_csr_int_flag_and_col() argument
171 write_csr_int_flag_and_col(void __iomem * csr_base_addr,u32 bank,u32 value) write_csr_int_flag_and_col() argument
177 read_csr_ring_srv_arb_en(void __iomem * csr_base_addr,u32 bank) read_csr_ring_srv_arb_en() argument
182 write_csr_ring_srv_arb_en(void __iomem * csr_base_addr,u32 bank,u32 value) write_csr_ring_srv_arb_en() argument
[all...]
H A Dadf_gen4_hw_csr_data.h37 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
39 ADF_RING_BUNDLE_SIZE * (bank) + \
41 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
43 ADF_RING_BUNDLE_SIZE * (bank) + \
45 #define READ_CSR_STAT(csr_base_addr, bank) \ argument
47 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_STAT)
48 #define READ_CSR_UO_STAT(csr_base_addr, bank) \ argument
50 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_UO_STAT)
51 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
53 ADF_RING_BUNDLE_SIZE * (bank)
54 READ_CSR_NE_STAT(csr_base_addr,bank) global() argument
57 READ_CSR_NF_STAT(csr_base_addr,bank) global() argument
60 READ_CSR_F_STAT(csr_base_addr,bank) global() argument
63 READ_CSR_C_STAT(csr_base_addr,bank) global() argument
66 READ_CSR_EXP_STAT(csr_base_addr,bank) global() argument
69 READ_CSR_EXP_INT_EN(csr_base_addr,bank) global() argument
72 WRITE_CSR_EXP_INT_EN(csr_base_addr,bank,value) global() argument
76 READ_CSR_RING_CONFIG(csr_base_addr,bank,ring) global() argument
80 WRITE_CSR_RING_CONFIG(csr_base_addr,bank,ring,value) global() argument
84 WRITE_CSR_RING_BASE(csr_base_addr,bank,ring,value) global() argument
101 read_base(void __iomem * csr_base_addr,u32 bank,u32 ring) read_base() argument
117 READ_CSR_RING_BASE(csr_base_addr,bank,ring) global() argument
120 WRITE_CSR_RING_HEAD(csr_base_addr,bank,ring,value) global() argument
124 WRITE_CSR_RING_TAIL(csr_base_addr,bank,ring,value) global() argument
128 READ_CSR_INT_EN(csr_base_addr,bank) global() argument
131 WRITE_CSR_INT_EN(csr_base_addr,bank,value) global() argument
135 READ_CSR_INT_FLAG(csr_base_addr,bank) global() argument
138 WRITE_CSR_INT_FLAG(csr_base_addr,bank,value) global() argument
142 READ_CSR_INT_SRCSEL(csr_base_addr,bank) global() argument
145 WRITE_CSR_INT_SRCSEL(csr_base_addr,bank) global() argument
149 WRITE_CSR_INT_SRCSEL_W_VAL(csr_base_addr,bank,value) global() argument
153 READ_CSR_INT_COL_EN(csr_base_addr,bank) global() argument
156 WRITE_CSR_INT_COL_EN(csr_base_addr,bank,value) global() argument
160 READ_CSR_INT_COL_CTL(csr_base_addr,bank) global() argument
163 WRITE_CSR_INT_COL_CTL(csr_base_addr,bank,value) global() argument
168 READ_CSR_INT_FLAG_AND_COL(csr_base_addr,bank) global() argument
172 WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr,bank,value) global() argument
177 READ_CSR_RING_SRV_ARB_EN(csr_base_addr,bank) global() argument
181 WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr,bank,value) global() argument
[all...]
H A Dadf_bank_state.c19 const char *name, void __iomem *base, u32 bank) in check_stat() argument
21 u32 actual_val = op(base, bank); in check_stat()
33 u32 bank, struct adf_bank_state *state, u32 num_rings) in bank_state_save() argument
37 state->ringstat0 = ops->read_csr_stat(base, bank); in bank_state_save()
38 state->ringuostat = ops->read_csr_uo_stat(base, bank); in bank_state_save()
39 state->ringestat = ops->read_csr_e_stat(base, bank); in bank_state_save()
40 state->ringnestat = ops->read_csr_ne_stat(base, bank); in bank_state_save()
41 state->ringnfstat = ops->read_csr_nf_stat(base, bank); in bank_state_save()
42 state->ringfstat = ops->read_csr_f_stat(base, bank); in bank_state_save()
43 state->ringcstat0 = ops->read_csr_c_stat(base, bank); in bank_state_save()
63 bank_state_restore(struct adf_hw_csr_ops * ops,void __iomem * base,u32 bank,struct adf_bank_state * state,u32 num_rings,int tx_rx_gap) bank_state_restore() argument
[all...]
H A Dadf_transport.c40 static int adf_reserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_reserve_ring() argument
42 spin_lock(&bank->lock); in adf_reserve_ring()
43 if (bank->ring_mask & (1 << ring)) { in adf_reserve_ring()
44 spin_unlock(&bank->lock); in adf_reserve_ring()
47 bank->ring_mask |= (1 << ring); in adf_reserve_ring()
48 spin_unlock(&bank->lock); in adf_reserve_ring()
52 static void adf_unreserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_unreserve_ring() argument
54 spin_lock(&bank->lock); in adf_unreserve_ring()
55 bank->ring_mask &= ~(1 << ring); in adf_unreserve_ring()
56 spin_unlock(&bank in adf_unreserve_ring()
59 adf_enable_ring_irq(struct adf_etr_bank_data * bank,u32 ring) adf_enable_ring_irq() argument
72 adf_disable_ring_irq(struct adf_etr_bank_data * bank,u32 ring) adf_disable_ring_irq() argument
162 struct adf_etr_bank_data *bank = ring->bank; adf_init_ring() local
225 struct adf_etr_bank_data *bank; adf_create_ring() local
306 struct adf_etr_bank_data *bank = ring->bank; adf_remove_ring() local
325 adf_ring_response_handler(struct adf_etr_bank_data * bank) adf_ring_response_handler() argument
343 struct adf_etr_bank_data *bank = (void *)bank_addr; adf_response_handler() local
370 adf_get_coalesc_timer(struct adf_etr_bank_data * bank,const char * section,u32 bank_num_in_accel) adf_get_coalesc_timer() argument
385 adf_init_bank(struct adf_accel_dev * accel_dev,struct adf_etr_bank_data * bank,u32 bank_num,void __iomem * csr_addr) adf_init_bank() argument
522 cleanup_bank(struct adf_etr_bank_data * bank) cleanup_bank() argument
[all...]
H A Dadf_gen2_hw_csr_data.c11 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument
13 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
16 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_head() argument
19 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
22 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument
24 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
27 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_tail() argument
30 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
33 static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank) in read_csr_e_stat() argument
35 return READ_CSR_E_STAT(csr_base_addr, bank); in read_csr_e_stat()
38 write_csr_ring_config(void __iomem * csr_base_addr,u32 bank,u32 ring,u32 value) write_csr_ring_config() argument
44 write_csr_ring_base(void __iomem * csr_base_addr,u32 bank,u32 ring,dma_addr_t addr) write_csr_ring_base() argument
50 write_csr_int_flag(void __iomem * csr_base_addr,u32 bank,u32 value) write_csr_int_flag() argument
55 write_csr_int_srcsel(void __iomem * csr_base_addr,u32 bank) write_csr_int_srcsel() argument
60 write_csr_int_col_en(void __iomem * csr_base_addr,u32 bank,u32 value) write_csr_int_col_en() argument
66 write_csr_int_col_ctl(void __iomem * csr_base_addr,u32 bank,u32 value) write_csr_int_col_ctl() argument
72 write_csr_int_flag_and_col(void __iomem * csr_base_addr,u32 bank,u32 value) write_csr_int_flag_and_col() argument
78 write_csr_ring_srv_arb_en(void __iomem * csr_base_addr,u32 bank,u32 value) write_csr_ring_srv_arb_en() argument
[all...]
H A Dadf_gen2_hw_csr_data.h30 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
31 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
33 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
34 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
36 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
37 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
39 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument
40 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
42 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument
47 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank))
53 WRITE_CSR_RING_HEAD(csr_base_addr,bank,ring,value) global() argument
56 WRITE_CSR_RING_TAIL(csr_base_addr,bank,ring,value) global() argument
59 WRITE_CSR_INT_FLAG(csr_base_addr,bank,value) global() argument
62 WRITE_CSR_INT_SRCSEL(csr_base_addr,bank) global() argument
69 WRITE_CSR_INT_COL_EN(csr_base_addr,bank,value) global() argument
72 WRITE_CSR_INT_COL_CTL(csr_base_addr,bank,value) global() argument
76 WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr,bank,value) global() argument
[all...]
H A Dadf_transport_debug.c51 struct adf_etr_bank_data *bank = ring->bank; in adf_ring_show() local
52 struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(bank->accel_dev); in adf_ring_show()
53 void __iomem *csr = ring->bank->csr_addr; in adf_ring_show()
58 head = csr_ops->read_csr_ring_head(csr, bank->bank_number, in adf_ring_show()
60 tail = csr_ops->read_csr_ring_tail(csr, bank->bank_number, in adf_ring_show()
62 empty = csr_ops->read_csr_e_stat(csr, bank->bank_number); in adf_ring_show()
67 seq_printf(sfile, "ring num %d, bank num %d\n", in adf_ring_show()
68 ring->ring_number, ring->bank->bank_number); in adf_ring_show()
111 ring->bank in adf_ring_debugfs_add()
128 struct adf_etr_bank_data *bank = sfile->private; adf_bank_start() local
143 struct adf_etr_bank_data *bank = sfile->private; adf_bank_next() local
154 struct adf_etr_bank_data *bank = sfile->private; adf_bank_show() local
198 adf_bank_debugfs_add(struct adf_etr_bank_data * bank) adf_bank_debugfs_add() argument
212 adf_bank_debugfs_rm(struct adf_etr_bank_data * bank) adf_bank_debugfs_rm() argument
[all...]
/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos.c62 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_mask() local
67 if (bank->eint_mask_offset) in exynos_irq_mask()
68 reg_mask = bank->pctl_offset + bank->eint_mask_offset; in exynos_irq_mask()
70 reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
72 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_mask()
73 dev_err(bank->gpio_chip.parent, in exynos_irq_mask()
78 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_mask()
80 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
82 writel(mask, bank in exynos_irq_mask()
93 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); exynos_irq_ack() local
116 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); exynos_irq_unmask() local
158 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); exynos_irq_set_type() local
215 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); exynos_irq_set_affinity() local
227 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); exynos_irq_request_resources() local
269 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); exynos_irq_release_resources() local
341 struct samsung_pin_bank *bank = d->pin_banks; exynos_eint_gpio_irq() local
399 exynos_eint_set_filter(struct samsung_pin_bank * bank,int filter) exynos_eint_set_filter() argument
416 struct samsung_pin_bank *bank; exynos_eint_gpio_init() local
479 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); gs101_wkup_irq_set_wake() local
525 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); exynos_wkup_irq_set_wake() local
699 struct samsung_pin_bank *bank = eintd->bank; exynos_irq_eint0_15() local
772 struct samsung_pin_bank *bank; exynos_eint_wkup_init() local
871 exynos_set_wakeup(struct samsung_pin_bank * bank) exynos_set_wakeup() argument
881 exynos_pinctrl_suspend(struct samsung_pin_bank * bank) exynos_pinctrl_suspend() argument
909 gs101_pinctrl_suspend(struct samsung_pin_bank * bank) gs101_pinctrl_suspend() argument
945 exynosautov920_pinctrl_suspend(struct samsung_pin_bank * bank) exynosautov920_pinctrl_suspend() argument
964 gs101_pinctrl_resume(struct samsung_pin_bank * bank) gs101_pinctrl_resume() argument
1002 exynos_pinctrl_resume(struct samsung_pin_bank * bank) exynos_pinctrl_resume() argument
1033 exynosautov920_pinctrl_resume(struct samsung_pin_bank * bank) exynosautov920_pinctrl_resume() argument
[all...]
H A Dpinctrl-samsung.c351 * given a pin number that is local to a pin controller, find out the pin bank
352 * and the register base of the pin bank.
356 struct samsung_pin_bank **bank) in pin_to_reg_bank() argument
368 if (bank) in pin_to_reg_bank()
369 *bank = b; in pin_to_reg_bank()
378 struct samsung_pin_bank *bank; in samsung_pinmux_setup() local
390 pin_to_reg_bank(drvdata, grp->pins[0], &reg, &pin_offset, &bank); in samsung_pinmux_setup()
391 type = bank->type; in samsung_pinmux_setup()
406 raw_spin_lock_irqsave(&bank->slock, flags); in samsung_pinmux_setup()
413 raw_spin_unlock_irqrestore(&bank in samsung_pinmux_setup()
442 struct samsung_pin_bank *bank; samsung_pinconf_rw() local
558 struct samsung_pin_bank *bank = gpiochip_get_data(gc); samsung_gpio_set_value() local
576 struct samsung_pin_bank *bank = gpiochip_get_data(gc); samsung_gpio_set() local
601 struct samsung_pin_bank *bank = gpiochip_get_data(gc); samsung_gpio_get() local
633 struct samsung_pin_bank *bank; samsung_gpio_set_direction() local
663 struct samsung_pin_bank *bank = gpiochip_get_data(gc); samsung_gpio_direction_input() local
687 struct samsung_pin_bank *bank = gpiochip_get_data(gc); samsung_gpio_direction_output() local
714 struct samsung_pin_bank *bank = gpiochip_get_data(gc); samsung_gpio_to_irq() local
727 struct samsung_pin_bank *bank = gpiochip_get_data(gc); samsung_add_pin_ranges() local
926 int pin, bank, ret; samsung_pinctrl_register() local
987 struct samsung_pin_bank *bank = drvdata->pin_banks; samsung_pinctrl_unregister() local
1012 struct samsung_pin_bank *bank = gpiochip_get_data(gc); samsung_gpio_set_pud() local
1032 struct samsung_pin_bank *bank = gpiochip_get_data(gc); samsung_gpio_set_config() local
1084 struct samsung_pin_bank *bank = drvdata->pin_banks; samsung_gpiolib_register() local
1134 struct samsung_pin_bank *bank; samsung_banks_node_put() local
1149 struct samsung_pin_bank *bank; samsung_banks_node_get() local
1191 struct samsung_pin_bank *bank; samsung_pinctrl_get_soc_data() local
1341 struct samsung_pin_bank *bank; samsung_pinctrl_suspend() local
1405 struct samsung_pin_bank *bank; samsung_pinctrl_resume() local
[all...]
H A Dpinctrl-samsung.h85 * @EINT_TYPE_NONE: bank does not support external interrupts
86 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
87 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
88 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
91 * in a pin bank can support external gpio interrupts or external wakeup
125 * struct samsung_pin_bank_type: pin bank type description
135 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
136 * @type: type of the bank (register offsets and bitfield widths)
137 * @pctl_offset: starting offset of the pin-bank registers.
138 * @pctl_res_idx: index of base address for pin-bank register
[all...]
/linux/tools/testing/selftests/gpio/
H A Dgpio-sim.sh25 BANK=`basename $FILE`
26 if [ "$BANK" = "live" -o "$BANK" = "dev_name" ]; then
30 LINES=`ls $CONFIGFS_DIR/$CHIP/$BANK/ | grep -E ^line`
33 if [ -e $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog ]; then
34 rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog || \
38 rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE || \
43 rmdir $CONFIGFS_DIR/$CHIP/$BANK
57 local BANK=$2
59 mkdir $CONFIGFS_DIR/$CHIP/$BANK
[all...]
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A Duncore-memory.json198 "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group these two modes together so that we can use four counters to track each of the major modes at one time. These major modes are used whenever there is an ISOCH txn in the memory controller. In these mode, only ISOCH transactions are processed.",
208 "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode is used to drain starved underfill reads. Regular reads and writes are blocked and only underfill reads will be processed.",
218 "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode is the default mode for the iMC, as reads are generally more critical to forward progress than writes.",
228 "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is triggered when the WPQ hits high occupancy and causes writes to be higher priority than reads. This can cause blips in the available read bandwidth in the system and temporarily increase read latencies in order to achieve better bus utilizations and higher bandwidth.",
553 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
558 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
562 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
567 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
572 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
577 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1
[all...]
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A Duncore-memory.json227 "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group these two modes together so that we can use four counters to track each of the major modes at one time. These major modes are used whenever there is an ISOCH txn in the memory controller. In these mode, only ISOCH transactions are processed.",
237 "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode is used to drain starved underfill reads. Regular reads and writes are blocked and only underfill reads will be processed.",
247 "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode is the default mode for the iMC, as reads are generally more critical to forward progress than writes.",
257 "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is triggered when the WPQ hits high occupancy and causes writes to be higher priority than reads. This can cause blips in the available read bandwidth in the system and temporarily increase read latencies in order to achieve better bus utilizations and higher bandwidth.",
582 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
587 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
591 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
596 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
601 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
606 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1
[all...]
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A Duncore-memory.json236 "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group these two modes together so that we can use four counters to track each of the major modes at one time. These major modes are used whenever there is an ISOCH txn in the memory controller. In these mode, only ISOCH transactions are processed.",
246 "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode is used to drain starved underfill reads. Regular reads and writes are blocked and only underfill reads will be processed.",
256 "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode is the default mode for the iMC, as reads are generally more critical to forward progress than writes.",
266 "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is triggered when the WPQ hits high occupancy and causes writes to be higher priority than reads. This can cause blips in the available read bandwidth in the system and temporarily increase read latencies in order to achieve better bus utilizations and higher bandwidth.",
591 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
596 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
600 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
605 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
610 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
615 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1
[all...]
/linux/drivers/net/phy/mscc/
H A Dmscc_macsec.c23 enum macsec_bank bank, u32 reg) in vsc8584_macsec_phy_read() argument
34 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_read()
36 if (bank >> 2 == 0x1) in vsc8584_macsec_phy_read()
38 bank &= 0x3; in vsc8584_macsec_phy_read()
40 bank = 0; in vsc8584_macsec_phy_read()
45 MSCC_PHY_MACSEC_19_TARGET(bank)); in vsc8584_macsec_phy_read()
62 enum macsec_bank bank, u32 reg, u32 val) in vsc8584_macsec_phy_write() argument
72 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_write()
74 if ((bank >> 2 == 0x1) || (bank >> in vsc8584_macsec_phy_write()
97 vsc8584_macsec_classification(struct phy_device * phydev,enum macsec_bank bank) vsc8584_macsec_classification() argument
107 vsc8584_macsec_flow_default_action(struct phy_device * phydev,enum macsec_bank bank,bool block) vsc8584_macsec_flow_default_action() argument
154 vsc8584_macsec_integrity_checks(struct phy_device * phydev,enum macsec_bank bank) vsc8584_macsec_integrity_checks() argument
176 vsc8584_macsec_block_init(struct phy_device * phydev,enum macsec_bank bank) vsc8584_macsec_block_init() argument
245 vsc8584_macsec_mac_init(struct phy_device * phydev,enum macsec_bank bank) vsc8584_macsec_mac_init() argument
374 enum macsec_bank bank = flow->bank; vsc8584_macsec_flow() local
449 vsc8584_macsec_find_flow(struct macsec_context * ctx,enum macsec_bank bank) vsc8584_macsec_find_flow() argument
464 enum macsec_bank bank = flow->bank; vsc8584_macsec_flow_enable() local
483 enum macsec_bank bank = flow->bank; vsc8584_macsec_flow_disable() local
524 enum macsec_bank bank = flow->bank; vsc8584_macsec_transformation() local
601 vsc8584_macsec_alloc_flow(struct vsc8531_private * priv,enum macsec_bank bank) vsc8584_macsec_alloc_flow() argument
[all...]
/linux/drivers/pinctrl/stm32/
H A Dpinctrl-stm32.c141 static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, u32 *alt);
176 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, in stm32_gpio_backup_value() argument
179 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); in stm32_gpio_backup_value()
180 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; in stm32_gpio_backup_value()
183 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_mode() argument
186 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | in stm32_gpio_backup_mode()
188 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; in stm32_gpio_backup_mode()
189 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; in stm32_gpio_backup_mode()
192 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_driving() argument
195 bank in stm32_gpio_backup_driving()
199 stm32_gpio_backup_speed(struct stm32_gpio_bank * bank,u32 offset,u32 speed) stm32_gpio_backup_speed() argument
206 stm32_gpio_backup_bias(struct stm32_gpio_bank * bank,u32 offset,u32 bias) stm32_gpio_backup_bias() argument
215 stm32_gpio_rif_valid(struct stm32_gpio_bank * bank,unsigned int gpio_nr) stm32_gpio_rif_valid() argument
237 stm32_gpio_rif_acquire_semaphore(struct stm32_gpio_bank * bank,unsigned int gpio_nr) stm32_gpio_rif_acquire_semaphore() argument
274 stm32_gpio_rif_release_semaphore(struct stm32_gpio_bank * bank,unsigned int gpio_nr) stm32_gpio_rif_release_semaphore() argument
289 __stm32_gpio_set(struct stm32_gpio_bank * bank,unsigned offset,int value) __stm32_gpio_set() argument
302 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); stm32_gpio_request() local
325 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); stm32_gpio_free() local
335 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); stm32_gpio_get() local
343 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); stm32_gpio_set() local
353 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); stm32_gpio_direction_output() local
363 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); stm32_gpio_to_irq() local
376 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); stm32_gpio_get_direction() local
396 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); stm32_gpio_init_valid_mask() local
447 struct stm32_gpio_bank *bank = d->domain->host_data; stm32_gpio_irq_trigger() local
469 struct stm32_gpio_bank *bank = d->domain->host_data; stm32_gpio_set_type() local
495 struct stm32_gpio_bank *bank = irq_data->domain->host_data; stm32_gpio_irq_request_resources() local
515 struct stm32_gpio_bank *bank = irq_data->domain->host_data; stm32_gpio_irq_release_resources() local
556 struct stm32_gpio_bank *bank = d->host_data; stm32_gpio_domain_activate() local
581 struct stm32_gpio_bank *bank = d->host_data; stm32_gpio_domain_alloc() local
620 struct stm32_gpio_bank *bank = d->host_data; stm32_gpio_domain_free() local
885 stm32_pmx_set_mode(struct stm32_gpio_bank * bank,int pin,u32 mode,u32 alt) stm32_pmx_set_mode() argument
927 stm32_pmx_get_mode(struct stm32_gpio_bank * bank,int pin,u32 * mode,u32 * alt) stm32_pmx_get_mode() argument
955 struct stm32_gpio_bank *bank; stm32_pmx_set_mux() local
987 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); stm32_pmx_gpio_set_direction() local
1024 stm32_pconf_set_driving(struct stm32_gpio_bank * bank,unsigned offset,u32 drive) stm32_pconf_set_driving() argument
1059 stm32_pconf_get_driving(struct stm32_gpio_bank * bank,unsigned int offset) stm32_pconf_get_driving() argument
1075 stm32_pconf_set_speed(struct stm32_gpio_bank * bank,unsigned offset,u32 speed) stm32_pconf_set_speed() argument
1110 stm32_pconf_get_speed(struct stm32_gpio_bank * bank,unsigned int offset) stm32_pconf_get_speed() argument
1126 stm32_pconf_set_bias(struct stm32_gpio_bank * bank,unsigned offset,u32 bias) stm32_pconf_set_bias() argument
1161 stm32_pconf_get_bias(struct stm32_gpio_bank * bank,unsigned int offset) stm32_pconf_get_bias() argument
1177 stm32_pconf_get(struct stm32_gpio_bank * bank,unsigned int offset,bool dir) stm32_pconf_get() argument
1203 struct stm32_gpio_bank *bank; stm32_pconf_parse_conf() local
1321 struct stm32_gpio_bank *bank; stm32_pconf_dbg_show() local
1399 stm32_pctrl_get_desc_pin_from_gpio(struct stm32_pinctrl * pctl,struct stm32_gpio_bank * bank,unsigned int offset) stm32_pctrl_get_desc_pin_from_gpio() argument
1424 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; stm32_gpiolib_register_bank() local
1750 struct stm32_gpio_bank *bank = &pctl->banks[i]; stm32_pctl_probe() local
1790 struct stm32_gpio_bank *bank = &pctl->banks[i]; stm32_pctl_probe() local
1806 struct stm32_gpio_bank *bank; stm32_pinctrl_restore_gpio_regs() local
[all...]
/linux/drivers/bus/
H A Duniphier-system-bus.c23 #define UNIPHIER_SBC_STRIDE 0x10 /* register stride to next bank */
25 #define UNIPHIER_SBC_BASE_DUMMY 0xffffffff /* data to squash bank 0, 1 */
35 struct uniphier_system_bus_bank bank[UNIPHIER_SBC_NR_BANKS]; member
39 int bank, u32 addr, u64 paddr, u32 size) in uniphier_system_bus_add_bank() argument
44 "range found: bank = %d, addr = %08x, paddr = %08llx, size = %08x\n", in uniphier_system_bus_add_bank()
45 bank, addr, paddr, size); in uniphier_system_bus_add_bank()
47 if (bank >= ARRAY_SIZE(priv->bank)) { in uniphier_system_bus_add_bank()
48 dev_err(priv->dev, "unsupported bank number %d\n", bank); in uniphier_system_bus_add_bank()
[all...]
/linux/arch/x86/kernel/cpu/mce/
H A Dthreshold.c35 void mce_inherit_storm(unsigned int bank) in mce_inherit_storm() argument
40 * Previous CPU owning this bank had put it into storm mode, in mce_inherit_storm()
42 * the worst (all recent polls of the bank found a valid error in mce_inherit_storm()
46 storm->banks[bank].history = ~0ull; in mce_inherit_storm()
47 storm->banks[bank].timestamp = jiffies; in mce_inherit_storm()
60 static void mce_handle_storm(unsigned int bank, bool on) in mce_handle_storm() argument
64 mce_intel_handle_storm(bank, on); in mce_handle_storm()
69 void cmci_storm_begin(unsigned int bank) in cmci_storm_begin() argument
73 __set_bit(bank, this_cpu_ptr(mce_poll_banks)); in cmci_storm_begin()
74 storm->banks[bank] in cmci_storm_begin()
84 cmci_storm_end(unsigned int bank) cmci_storm_end() argument
[all...]
H A Damd.c131 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) in smca_get_bank_type() argument
135 if (bank >= MAX_NR_BANKS) in smca_get_bank_type()
138 b = &per_cpu(smca_banks, cpu)[bank]; in smca_get_bank_type()
212 * So to define a unique name for each bank, we use a temp c-string to append
222 /* This block's number within its bank. */
224 /* MCA bank number that contains this block. */
225 unsigned int bank; member
226 /* CPU which controls this block's MCA bank. */
232 /* Bank can generate an interrupt. */
238 /* List of threshold blocks within this block's MCA bank
267 smca_set_misc_banks_map(unsigned int bank,unsigned int cpu) smca_set_misc_banks_map() argument
289 smca_configure(unsigned int bank,unsigned int cpu) smca_configure() argument
378 lvt_interrupt_supported(unsigned int bank,u32 msr_high_bits) lvt_interrupt_supported() argument
528 smca_get_block_address(unsigned int bank,unsigned int block,unsigned int cpu) smca_get_block_address() argument
541 get_block_address(u32 current_addr,u32 low,u32 high,unsigned int bank,unsigned int block,unsigned int cpu) get_block_address() argument
569 prepare_threshold_block(unsigned int bank,unsigned int block,u32 addr,int offset,u32 misc_high) prepare_threshold_block() argument
641 disable_err_thresholding(struct cpuinfo_x86 * c,unsigned int bank) disable_err_thresholding() argument
683 unsigned int bank, block, cpu = smp_processor_id(); mce_amd_feature_init() local
788 __log_error(unsigned int bank,u64 status,u64 addr,u64 misc) __log_error() argument
832 _log_error_bank(unsigned int bank,u32 msr_stat,u32 msr_addr,u64 misc) _log_error_bank() argument
850 _log_error_deferred(unsigned int bank,u32 misc) _log_error_deferred() argument
877 log_error_deferred(unsigned int bank) log_error_deferred() argument
893 unsigned int bank; amd_deferred_error_interrupt() local
899 log_error_thresholding(unsigned int bank,u64 misc) log_error_thresholding() argument
935 unsigned int bank, cpu = smp_processor_id(); amd_threshold_interrupt() local
1103 get_name(unsigned int cpu,unsigned int bank,struct threshold_block * b) get_name() argument
1141 allocate_threshold_blocks(unsigned int cpu,struct threshold_bank * tb,unsigned int bank,unsigned int block,u32 address) allocate_threshold_blocks() argument
1218 threshold_create_bank(struct threshold_bank ** bp,unsigned int cpu,unsigned int bank) threshold_create_bank() argument
1261 deallocate_threshold_blocks(struct threshold_bank * bank) deallocate_threshold_blocks() argument
1273 threshold_remove_bank(struct threshold_bank * bank) threshold_remove_bank() argument
1287 unsigned int bank, numbanks = this_cpu_read(mce_num_banks); __threshold_remove_device() local
1329 unsigned int numbanks, bank; mce_threshold_create_device() local
[all...]
H A Dintel.c31 * CMCI can be delivered to multiple cpus that share a machine check bank
32 * so we need to designate a single cpu to process errors logged in each bank
61 * MCi_CTL2 threshold for each bank when there is no storm.
62 * Default value for each bank may have been set by BIOS.
71 * bank because both corrected and uncorrected errors may be logged
72 * in the same bank and signalled with CMCI. The threshold only applies
138 static void cmci_set_threshold(int bank, int thresh) in cmci_set_threshold() argument
144 rdmsrq(MSR_IA32_MCx_CTL2(bank), val); in cmci_set_threshold()
146 wrmsrq(MSR_IA32_MCx_CTL2(bank), val | thresh); in cmci_set_threshold()
150 void mce_intel_handle_storm(int bank, boo argument
176 cmci_skip_bank(int bank,u64 * val) cmci_skip_bank() argument
230 cmci_claim_bank(int bank,u64 val,int bios_zero_thresh,int * bios_wrong_thresh) cmci_claim_bank() argument
321 __cmci_disable_bank(int bank) __cmci_disable_bank() argument
384 cmci_disable_bank(int bank) cmci_disable_bank() argument
[all...]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos9810-pinctrl.dtsi12 etc1: etc1-gpio-bank {
20 gpa0: gpa0-gpio-bank {
37 gpa1: gpa1-gpio-bank {
54 gpa2: gpa2-gpio-bank {
71 gpa3: gpa3-gpio-bank {
88 gpa4: gpa4-gpio-bank {
96 gpq0: gpq0-gpio-bank {
106 gpb0: gpb0-gpio-bank {
114 gpb1: gpb1-gpio-bank {
122 gpb2: gpb2-gpio-bank {
[all...]
/linux/drivers/pinctrl/meson/
H A Dpinctrl-amlogic-a4.c54 * partial bank(subordinate) pins mux config use other bank(main) mux registgers
55 * m_bank_id: the main bank which pin_id from 0, but register bit not from bit 0
56 * m_bit_offs: bit offset the main bank mux register
57 * sid: start pin_id of subordinate bank
58 * eid: end pin_id of subordinate bank
176 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); in aml_pctl_set_function() local
180 unsigned int offset = bank->mux_bit_offs; in aml_pctl_set_function()
184 if (bank->p_mux) { in aml_pctl_set_function()
185 p_mux = bank in aml_pctl_set_function()
281 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); aml_calc_reg_and_bit() local
295 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); aml_pinconf_get_pull() local
329 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); aml_pinconf_get_drive_strength() local
368 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); aml_pinconf_get_gpio_bit() local
452 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); aml_pinconf_disable_bias() local
465 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); aml_pinconf_enable_bias() local
487 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); aml_pinconf_set_drive_strength() local
522 struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc); aml_pinconf_set_gpio_bit() local
809 aml_gpio_calc_reg_and_bit(struct aml_gpio_bank * bank,unsigned int reg_type,unsigned int gpio,unsigned int * reg,unsigned int * bit) aml_gpio_calc_reg_and_bit() argument
824 struct aml_gpio_bank *bank = gpiochip_get_data(chip); aml_gpio_get_direction() local
839 struct aml_gpio_bank *bank = gpiochip_get_data(chip); aml_gpio_direction_input() local
850 struct aml_gpio_bank *bank = gpiochip_get_data(chip); aml_gpio_direction_output() local
867 struct aml_gpio_bank *bank = gpiochip_get_data(chip); aml_gpio_set() local
878 struct aml_gpio_bank *bank = gpiochip_get_data(chip); aml_gpio_get() local
900 init_bank_register_bit(struct aml_pinctrl * info,struct aml_gpio_bank * bank) init_bank_register_bit() argument
931 struct aml_gpio_bank *bank = &info->banks[bank_nr]; aml_gpiolib_register_bank() local
985 int i = 0, j = 0, k = 0, bank; aml_pctl_probe_dt() local
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