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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-nominal.dtsi7 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
13 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
19 assigned-clock-rates = <0>, <0>,
28 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
29 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
30 assigned-clock-rates = <800000000>;
34 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
36 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
38 assigned-clock-rates = <800000000>, <800000000>;
42 assigned
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H A Dimx8mm-overdrive.dtsi4 assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
6 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
7 assigned-clock-rates = <0>, <1000000000>;
11 assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
13 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
14 assigned-clock-rates = <0>, <1000000000>;
18 assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
22 assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
25 assigned-clock-rates = <750000000>,
H A Dimx8-ss-dma.dtsi34 assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;
35 assigned-clock-rates = <60000000>;
52 assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;
53 assigned-clock-rates = <60000000>;
70 assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>;
71 assigned-clock-rates = <60000000>;
88 assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>;
89 assigned-clock-rates = <60000000>;
102 assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
103 assigned
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H A Dimx8mp.dtsi758 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
763 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
768 assigned-clock-rates = <0>, <0>,
819 assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,
822 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
825 assigned-clock-rates = <1000000000>,
835 assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
837 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
839 assigned-clock-rates = <400000000>,
855 assigned
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H A Dimx8mm-evk.dtsi462 assigned-clocks = <&clk IMX8MM_CLK_CLKO1>;
463 assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
464 assigned-clock-rates = <24000000>;
489 assigned-clocks = <&clk IMX8MM_CLK_PDM>;
490 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
491 assigned-clock-rates = <196608000>;
538 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
540 assigned-clock-rates = <10000000>, <250000000>;
541 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
552 assigned
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/linux/Documentation/process/
H A Dcve.rst8 regards to the kernel project, and CVE numbers were very often assigned
21 A list of all assigned CVEs for the Linux kernel can be found in the
24 assigned CVEs, please `subscribe
32 for CVE number assignments and have CVE numbers automatically assigned
45 should have a CVE assigned to it, please email them at <cve@kernel.org>
53 No CVEs will be automatically assigned for unfixed security issues in
57 have a CVE assigned before an issue is resolved with a commit, please
59 identifier assigned from their batch of reserved identifiers.
61 No CVEs will be assigned for any issue found in a version of the kernel
66 Disputes of assigned CVE
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/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra-audio-graph-card.yaml36 assigned-clocks:
40 assigned-clock-parents:
44 assigned-clock-rates:
64 - assigned-clocks
65 - assigned-clock-parents
80 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
83 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
84 assigned-clock-rates = <368640000>, <49152000>, <12288000>;
102 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
103 assigned
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H A Dnvidia,tegra210-ahub.yaml44 assigned-clocks:
47 assigned-clock-parents:
50 assigned-clock-rates:
123 - assigned-clocks
124 - assigned-clock-parents
140 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
141 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
177 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
178 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
179 assigned
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H A Dbrcm,cygnus-audio.txt13 - assigned-clocks: PLL and leaf clocks
14 - assigned-clock-parents: parent clocks of the assigned clocks
16 - assigned-clock-rates: List of clock frequencies of the
17 assigned clocks
36 assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>,
40 assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>;
41 assigned-clock-rates = <1769470191>,
H A Dnvidia,tegra210-dmic.yaml46 assigned-clocks:
49 assigned-clock-parents:
52 assigned-clock-rates:
80 - assigned-clocks
81 - assigned-clock-parents
94 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
95 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
96 assigned-clock-rates = <3072000>;
H A Dnvidia,tegra186-dspk.yaml46 assigned-clocks:
49 assigned-clock-parents:
52 assigned-clock-rates:
80 - assigned-clocks
81 - assigned-clock-parents
95 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
96 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
97 assigned-clock-rates = <12288000>;
H A Dnvidia,tegra210-i2s.yaml60 assigned-clocks:
64 assigned-clock-parents:
68 assigned-clock-rates:
97 - assigned-clocks
98 - assigned-clock-parents
111 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
112 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
113 assigned-clock-rates = <1536000>;
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7ulp.dtsi154 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
155 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
156 assigned-clock-rates = <24000000>;
166 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
167 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
168 assigned-clock-rates = <48000000>;
175 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
176 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
263 assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
264 assigned
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/linux/drivers/clk/
H A Dclk-conf.c21 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents()
28 rc = of_parse_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents()
50 rc = of_parse_phandle_with_args(node, "assigned-clocks", in __set_clk_parents()
63 pr_warn("clk: couldn't get assigned clock %d for %pOF\n", in __set_clk_parents()
90 count = of_property_count_u32_elems(node, "assigned-clock-rates"); in __set_clk_rates()
91 count_64 = of_property_count_u64_elems(node, "assigned-clock-rates-u64"); in __set_clk_rates()
99 "assigned-clock-rates-u64", in __set_clk_rates()
106 rc = of_property_read_u32_array(node, "assigned-clock-rates", in __set_clk_rates()
124 rc = of_parse_phandle_with_args(node, "assigned-clocks", in __set_clk_rates()
159 * of_clk_set_defaults() - parse and set assigned clock
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/linux/Documentation/devicetree/bindings/display/msm/
H A Ddsi-controller-main.yaml109 assigned-clocks:
118 assigned-clock-parents:
248 - assigned-clocks
249 - assigned-clock-parents
273 - assigned-clocks
274 - assigned-clock-parents
298 - assigned-clocks
299 - assigned-clock-parents
322 - assigned-clocks
323 - assigned
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/linux/arch/arm64/boot/dts/ti/
H A Dk3-j784s4-j742s2-main-common.dtsi125 assigned-clocks = <&k3_clks 157 34>;
126 assigned-clock-parents = <&k3_clks 157 63>;
290 assigned-clocks = <&k3_clks 97 2>;
291 assigned-clock-parents = <&k3_clks 97 3>;
302 assigned-clocks = <&k3_clks 98 2>;
303 assigned-clock-parents = <&k3_clks 98 3>;
314 assigned-clocks = <&k3_clks 99 2>;
315 assigned-clock-parents = <&k3_clks 99 3>;
326 assigned-clocks = <&k3_clks 100 2>;
327 assigned
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H A Dk3-j721s2-mcu-wakeup.dtsi173 assigned-clocks = <&k3_clks 35 1>;
174 assigned-clock-parents = <&k3_clks 35 2>;
188 assigned-clocks = <&k3_clks 83 1>;
189 assigned-clock-parents = <&k3_clks 83 2>;
202 assigned-clocks = <&k3_clks 84 1>;
203 assigned-clock-parents = <&k3_clks 84 2>;
216 assigned-clocks = <&k3_clks 85 1>;
217 assigned-clock-parents = <&k3_clks 85 2>;
230 assigned-clocks = <&k3_clks 86 1>;
231 assigned
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H A Dk3-j784s4-j742s2-mcu-wakeup-common.dtsi172 assigned-clocks = <&k3_clks 35 2>;
173 assigned-clock-parents = <&k3_clks 35 3>;
187 assigned-clocks = <&k3_clks 117 2>;
188 assigned-clock-parents = <&k3_clks 117 3>;
201 assigned-clocks = <&k3_clks 118 2>;
202 assigned-clock-parents = <&k3_clks 118 3>;
215 assigned-clocks = <&k3_clks 119 2>;
216 assigned-clock-parents = <&k3_clks 119 3>;
229 assigned-clocks = <&k3_clks 120 2>;
230 assigned
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H A Dk3-j721e-mcu-wakeup.dtsi116 assigned-clocks = <&k3_clks 35 1>;
117 assigned-clock-parents = <&k3_clks 35 2>;
131 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>;
132 assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 322 1>;
145 assigned-clocks = <&k3_clks 72 1>;
146 assigned-clock-parents = <&k3_clks 72 2>;
159 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>;
160 assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 323 1>;
173 assigned-clocks = <&k3_clks 74 1>;
174 assigned
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H A Dk3-j721s2-main.dtsi229 assigned-clocks = <&k3_clks 63 1>;
230 assigned-clock-parents = <&k3_clks 63 2>;
241 assigned-clocks = <&k3_clks 64 1>;
242 assigned-clock-parents = <&k3_clks 64 2>;
253 assigned-clocks = <&k3_clks 65 1>;
254 assigned-clock-parents = <&k3_clks 65 2>;
265 assigned-clocks = <&k3_clks 66 1>;
266 assigned-clock-parents = <&k3_clks 66 2>;
277 assigned-clocks = <&k3_clks 67 1>;
278 assigned
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/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-clk-ccf.dtsi170 assigned-clocks = <&zynqmp_clk GEM_TSU>;
177 assigned-clocks = <&zynqmp_clk GEM_TSU>;
184 assigned-clocks = <&zynqmp_clk GEM_TSU>;
191 assigned-clocks = <&zynqmp_clk GEM_TSU>;
220 assigned-clocks = <&zynqmp_clk SDIO0_REF>;
225 assigned-clocks = <&zynqmp_clk SDIO1_REF>;
254 assigned-clocks = <&zynqmp_clk UART0_REF>;
259 assigned-clocks = <&zynqmp_clk UART1_REF>;
264 assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
273 assigned
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos4412-odroid-common.dtsi129 assigned-clocks = <&clock CLK_FOUT_EPLL>;
130 assigned-clock-rates = <45158401>;
134 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
140 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
143 assigned-clock-rates = <0>, <0>,
211 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
213 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
214 assigned-clock-rates = <0>, <176000000>;
219 assigned-clocks = <&clock CLK_MOUT_FIMC1>,
221 assigned
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/linux/arch/mips/boot/dts/img/
H A Dpistachio.dtsi51 assigned-clocks = <&clk_periph PERIPH_CLK_I2C0_PRE_DIV>,
53 assigned-clock-rates = <100000000>, <33333334>;
69 assigned-clocks = <&clk_periph PERIPH_CLK_I2C1_PRE_DIV>,
71 assigned-clock-rates = <100000000>, <33333334>;
87 assigned-clocks = <&clk_periph PERIPH_CLK_I2C2_PRE_DIV>,
89 assigned-clock-rates = <100000000>, <33333334>;
105 assigned-clocks = <&clk_periph PERIPH_CLK_I2C3_PRE_DIV>,
107 assigned-clock-rates = <100000000>, <33333334>;
141 assigned-clocks = <&clk_core CLK_I2S_DIV>;
142 assigned
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/linux/Documentation/devicetree/bindings/iio/adc/
H A Dnxp,imx8qxp-adc.yaml33 assigned-clocks:
36 assigned-clock-rates:
57 - assigned-clocks
58 - assigned-clock-rates
78 assigned-clocks = <&clk IMX_SC_R_ADC_0>;
79 assigned-clock-rates = <24000000>;
/linux/tools/perf/pmu-events/arch/x86/amdzen1/
H A Dfloating-point.json5 "BriefDescription": "Total number multi-pipe uOps assigned to all pipes.",
6 "PublicDescription": "The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to all pipes.",
12 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 3.",
13 "PublicDescription": "The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 3.",
19 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 2.",
20 "PublicDescription": "The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 2.",
26 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 1.",
27 "PublicDescription": "The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned to pipe 1.",
33 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 0.",
34 "PublicDescription": "The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number multi-pipe uOps assigned t
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