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/linux/drivers/accel/habanalabs/gaudi/
H A Dgaudi_security.c489 u32 pb_addr, mask; in gaudi_init_mme_protection_bits() local
515 mask = 1U << ((mmMME0_CTRL_RESET & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
516 mask |= 1U << ((mmMME0_CTRL_QM_STALL & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
517 mask |= 1U << ((mmMME0_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
518 mask |= 1U << ((mmMME0_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
519 mask |= 1U << ((mmMME0_CTRL_INTR_CAUSE & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
520 mask |= 1U << ((mmMME0_CTRL_INTR_MASK & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
521 mask |= 1U << ((mmMME0_CTRL_LOG_SHADOW & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
522 mask |= 1U << ((mmMME0_CTRL_PCU_RL_DESC0 & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
523 mask |= 1U << ((mmMME0_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
[all …]
/linux/drivers/accel/habanalabs/goya/
H A Dgoya_security.c30 u32 pb_addr, mask; in goya_init_mme_protection_bits() local
69 mask = 1 << ((mmMME_DUMMY & 0x7F) >> 2); in goya_init_mme_protection_bits()
70 mask |= 1 << ((mmMME_RESET & 0x7F) >> 2); in goya_init_mme_protection_bits()
71 mask |= 1 << ((mmMME_STALL & 0x7F) >> 2); in goya_init_mme_protection_bits()
72 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); in goya_init_mme_protection_bits()
73 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); in goya_init_mme_protection_bits()
74 mask |= 1 << ((mmMME_DBGMEM_ADD & 0x7F) >> 2); in goya_init_mme_protection_bits()
75 mask |= 1 << ((mmMME_DBGMEM_DATA_WR & 0x7F) >> 2); in goya_init_mme_protection_bits()
76 mask |= 1 << ((mmMME_DBGMEM_DATA_RD & 0x7F) >> 2); in goya_init_mme_protection_bits()
77 mask |= 1 << ((mmMME_DBGMEM_CTRL & 0x7F) >> 2); in goya_init_mme_protection_bits()
[all …]
/linux/drivers/video/fbdev/riva/
H A Dnvreg.h31 #define MASKEXPAND(mask) BITMASK(1?mask,0?mask) argument
33 /* Macro to set specific bitfields (mask has to be a macro x:y) ! */
34 #define SetBF(mask,value) ((value) << (0?mask)) argument
35 #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) ) argument
37 #define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \ argument
38 | SetBF(mask,value)))
51 #define DEVICE_DEF(device,mask,value) \ argument
52 SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value)
53 #define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value) argument
54 #define DEVICE_MASK(device,mask) MASKEXPAND(NV_##device##_##mask) argument
[all …]
/linux/arch/s390/kernel/
H A Dfpu.c18 int mask; in __kernel_fpu_begin() local
24 flags &= state->hdr.mask; in __kernel_fpu_begin()
32 mask = flags & KERNEL_VXR; in __kernel_fpu_begin()
33 if (mask == KERNEL_VXR) { in __kernel_fpu_begin()
38 if (mask == KERNEL_VXR_MID) { in __kernel_fpu_begin()
42 mask = flags & KERNEL_VXR_LOW; in __kernel_fpu_begin()
43 if (mask) { in __kernel_fpu_begin()
44 if (mask == KERNEL_VXR_LOW) in __kernel_fpu_begin()
46 else if (mask == KERNEL_VXR_V0V7) in __kernel_fpu_begin()
51 mask = flags & KERNEL_VXR_HIGH; in __kernel_fpu_begin()
[all …]
/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/
H A Ddr_ste.c11 u8 mask[DR_STE_SIZE_MASK]; member
40 /* Mask tag using byte mask, bit per byte */ in mlx5dr_ste_calc_hash_index()
79 memcpy(hw_ste->mask, bit_mask, DR_STE_SIZE_MASK); in mlx5dr_ste_set_bit_mask()
85 memset(&hw_ste->mask, 0, sizeof(hw_ste->mask)); in dr_ste_set_always_hit()
91 hw_ste->mask[0] = 0; in dr_ste_set_always_miss()
700 "Partial ip_version mask with src/dst IP is not supported\n"); in dr_ste_build_pre_check_spec()
706 "Partial/no ethertype mask with src/dst IP is not supported\n"); in dr_ste_build_pre_check_spec()
715 struct mlx5dr_match_param *mask, in mlx5dr_ste_build_pre_check() argument
722 if (mask->misc.source_port && mask->misc.source_port != 0xffff) { in mlx5dr_ste_build_pre_check()
724 "Partial mask source_port is not supported\n"); in mlx5dr_ste_build_pre_check()
[all …]
H A Ddr_matcher.c116 dr_mask_is_tnl_vxlan_gpe(struct mlx5dr_match_param *mask, in dr_mask_is_tnl_vxlan_gpe() argument
119 return dr_mask_is_vxlan_gpe_set(&mask->misc3) && in dr_mask_is_tnl_vxlan_gpe()
157 dr_mask_is_tnl_geneve(struct mlx5dr_match_param *mask, in dr_mask_is_tnl_geneve() argument
160 return dr_mask_is_tnl_geneve_set(&mask->misc) && in dr_mask_is_tnl_geneve()
174 static bool dr_mask_is_tnl_gtpu(struct mlx5dr_match_param *mask, in dr_mask_is_tnl_gtpu() argument
177 return dr_mask_is_tnl_gtpu_set(&mask->misc3) && in dr_mask_is_tnl_gtpu()
186 static bool dr_mask_is_tnl_gtpu_dw_0(struct mlx5dr_match_param *mask, in dr_mask_is_tnl_gtpu_dw_0() argument
189 return mask->misc3.gtpu_dw_0 && in dr_mask_is_tnl_gtpu_dw_0()
198 static bool dr_mask_is_tnl_gtpu_teid(struct mlx5dr_match_param *mask, in dr_mask_is_tnl_gtpu_teid() argument
201 return mask->misc3.gtpu_teid && in dr_mask_is_tnl_gtpu_teid()
[all …]
/linux/include/sound/
H A Dpcm_params.h26 static inline void snd_mask_none(struct snd_mask *mask) in snd_mask_none() argument
28 memset(mask, 0, sizeof(*mask)); in snd_mask_none()
31 static inline void snd_mask_any(struct snd_mask *mask) in snd_mask_any() argument
33 memset(mask, 0xff, SNDRV_MASK_SIZE * sizeof(u_int32_t)); in snd_mask_any()
36 static inline int snd_mask_empty(const struct snd_mask *mask) in snd_mask_empty() argument
40 if (mask->bits[i]) in snd_mask_empty()
45 static inline unsigned int snd_mask_min(const struct snd_mask *mask) in snd_mask_min() argument
49 if (mask->bits[i]) in snd_mask_min()
50 return __ffs(mask->bits[i]) + (i << 5); in snd_mask_min()
55 static inline unsigned int snd_mask_max(const struct snd_mask *mask) in snd_mask_max() argument
[all …]
/linux/drivers/mfd/
H A Dwm8350-irq.c37 int mask; member
45 .mask = WM8350_OC_LS_EINT,
51 .mask = WM8350_UV_DC1_EINT,
56 .mask = WM8350_UV_DC2_EINT,
61 .mask = WM8350_UV_DC3_EINT,
66 .mask = WM8350_UV_DC4_EINT,
71 .mask = WM8350_UV_DC5_EINT,
76 .mask = WM8350_UV_DC6_EINT,
81 .mask = WM8350_UV_LDO1_EINT,
86 .mask = WM8350_UV_LDO2_EINT,
[all …]
H A Dda9052-irq.c38 .mask = DA9052_IRQ_MASK_POS_1,
42 .mask = DA9052_IRQ_MASK_POS_2,
46 .mask = DA9052_IRQ_MASK_POS_3,
50 .mask = DA9052_IRQ_MASK_POS_4,
54 .mask = DA9052_IRQ_MASK_POS_5,
58 .mask = DA9052_IRQ_MASK_POS_6,
62 .mask = DA9052_IRQ_MASK_POS_7,
66 .mask = DA9052_IRQ_MASK_POS_8,
70 .mask = DA9052_IRQ_MASK_POS_1,
74 .mask = DA9052_IRQ_MASK_POS_2,
[all …]
H A Dwm831x-irq.c28 int mask; member
35 .mask = WM831X_TEMP_THW_EINT,
40 .mask = WM831X_GP1_EINT,
45 .mask = WM831X_GP2_EINT,
50 .mask = WM831X_GP3_EINT,
55 .mask = WM831X_GP4_EINT,
60 .mask = WM831X_GP5_EINT,
65 .mask = WM831X_GP6_EINT,
70 .mask = WM831X_GP7_EINT,
75 .mask = WM831X_GP8_EINT,
[all …]
H A Dpalmas.c48 .mask = TPS65917_RESERVED,
51 .mask = TPS65917_INT1_STATUS_PWRON,
54 .mask = TPS65917_INT1_STATUS_LONG_PRESS_KEY,
57 .mask = TPS65917_RESERVED,
60 .mask = TPS65917_INT1_STATUS_PWRDOWN,
63 .mask = TPS65917_INT1_STATUS_HOTDIE,
66 .mask = TPS65917_INT1_STATUS_VSYS_MON,
69 .mask = TPS65917_RESERVED,
73 .mask = TPS65917_RESERVED,
77 .mask = TPS65917_INT2_STATUS_OTP_ERROR,
[all …]
/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/
H A Dbwc_complex.c6 #define HWS_CLEAR_MATCH_PARAM(mask, field) \ argument
7 MLX5_SET(fte_match_param, (mask)->match_buf, field, 0)
24 struct mlx5hws_match_parameters *mask) in mlx5hws_bwc_match_params_is_complex() argument
35 mask->match_buf, in mlx5hws_bwc_match_params_is_complex()
36 mask->match_sz, in mlx5hws_bwc_match_params_is_complex()
70 struct mlx5hws_match_parameters *mask) in hws_bwc_matcher_complex_params_clear_fld() argument
87 HWS_CLEAR_MATCH_PARAM(mask, outer_headers.smac_47_16); in hws_bwc_matcher_complex_params_clear_fld()
90 HWS_CLEAR_MATCH_PARAM(mask, inner_headers.smac_47_16); in hws_bwc_matcher_complex_params_clear_fld()
93 HWS_CLEAR_MATCH_PARAM(mask, outer_headers.smac_15_0); in hws_bwc_matcher_complex_params_clear_fld()
96 HWS_CLEAR_MATCH_PARAM(mask, inner_headers.smac_15_0); in hws_bwc_matcher_complex_params_clear_fld()
[all …]
/linux/drivers/platform/mellanox/
H A Dmlx-platform.c433 .mask = MLXPLAT_CPLD_I2C_CAP_MASK,
448 .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX,
703 .mask = BIT(0),
709 .mask = BIT(1),
719 .mask = BIT(0),
725 .mask = BIT(1),
734 .mask = BIT(0),
741 .mask = BIT(1),
751 .mask = BIT(0),
757 .mask = BIT(1),
[all …]
/linux/arch/powerpc/sysdev/
H A Dfsl_rcpm.c30 unsigned int mask = 1 << hw_cpu; in rcpm_v1_irq_mask() local
32 setbits32(&rcpm_v1_regs->cpmimr, mask); in rcpm_v1_irq_mask()
33 setbits32(&rcpm_v1_regs->cpmcimr, mask); in rcpm_v1_irq_mask()
34 setbits32(&rcpm_v1_regs->cpmmcmr, mask); in rcpm_v1_irq_mask()
35 setbits32(&rcpm_v1_regs->cpmnmimr, mask); in rcpm_v1_irq_mask()
41 unsigned int mask = 1 << hw_cpu; in rcpm_v2_irq_mask() local
43 setbits32(&rcpm_v2_regs->tpmimr0, mask); in rcpm_v2_irq_mask()
44 setbits32(&rcpm_v2_regs->tpmcimr0, mask); in rcpm_v2_irq_mask()
45 setbits32(&rcpm_v2_regs->tpmmcmr0, mask); in rcpm_v2_irq_mask()
46 setbits32(&rcpm_v2_regs->tpmnmimr0, mask); in rcpm_v2_irq_mask()
[all …]
H A Dipic.c35 .mask = IPIC_SIMSR_H,
42 .mask = IPIC_SIMSR_H,
49 .mask = IPIC_SIMSR_H,
56 .mask = IPIC_SIMSR_H,
63 .mask = IPIC_SIMSR_H,
70 .mask = IPIC_SIMSR_H,
77 .mask = IPIC_SIMSR_H,
84 .mask = IPIC_SIMSR_H,
91 .mask = IPIC_SIMSR_H,
98 .mask = IPIC_SIMSR_H,
[all …]
/linux/drivers/video/fbdev/
H A Dc2p_core.h23 unsigned int shift, u32 mask) in _transp() argument
25 u32 t = (d[i1] ^ (d[i2] >> shift)) & mask; in _transp()
62 u32 mask = get_mask(n); in transp8() local
67 _transp(d, 0, 1, n, mask); in transp8()
69 _transp(d, 2, 3, n, mask); in transp8()
71 _transp(d, 4, 5, n, mask); in transp8()
73 _transp(d, 6, 7, n, mask); in transp8()
78 _transp(d, 0, 2, n, mask); in transp8()
79 _transp(d, 1, 3, n, mask); in transp8()
81 _transp(d, 4, 6, n, mask); in transp8()
[all …]
/linux/drivers/infiniband/sw/rxe/
H A Drxe_opcode.c17 .mask = {
24 .mask = {
31 .mask = {
40 .mask = {
49 .mask = {
55 .mask = {
61 .mask = {
67 .mask = {
73 .mask = {
81 .mask = {
[all …]
/linux/net/netlabel/
H A Dnetlabel_addrlist.c52 if (iter->valid && (addr & iter->mask) == iter->addr) in netlbl_af4list_search()
61 * @mask: IPv4 address mask
71 __be32 mask, in netlbl_af4list_search_exact() argument
77 if (iter->valid && iter->addr == addr && iter->mask == mask) in netlbl_af4list_search_exact()
103 ipv6_masked_addr_cmp(&iter->addr, &iter->mask, addr) == 0) in netlbl_af6list_search()
112 * @mask: IPv6 address mask
122 const struct in6_addr *mask, in netlbl_af6list_search_exact() argument
130 ipv6_addr_equal(&iter->mask, mask)) in netlbl_af6list_search_exact()
154 iter->addr == entry->addr && iter->mask == entry->mask) in netlbl_af4list_add()
159 * address mask such that the entry with the widest mask (smallest in netlbl_af4list_add()
[all …]
/linux/drivers/scsi/aic7xxx/
H A Daic7xxx.reg107 mask STIMESEL 0x18
132 mask PHASE_MASK CDI|IOI|MSGI
133 mask P_DATAOUT 0x00
134 mask P_DATAIN IOI
135 mask P_DATAOUT_DT P_DATAOUT|MSGI
136 mask P_DATAIN_DT P_DATAIN|MSGI
137 mask P_COMMAND CDI
138 mask P_MESGOUT CDI|MSGI
139 mask P_STATUS CDI|IOI
140 mask P_MESGIN CDI|IOI|MSGI
[all …]
/linux/arch/sh/include/asm/
H A Dbitops-cas.h16 unsigned mask, old; in set_bit() local
20 mask = 1U << (nr & 0x1f); in set_bit()
23 while (__bo_cas(a, old, old|mask) != old); in set_bit()
28 unsigned mask, old; in clear_bit() local
32 mask = 1U << (nr & 0x1f); in clear_bit()
35 while (__bo_cas(a, old, old&~mask) != old); in clear_bit()
40 unsigned mask, old; in change_bit() local
44 mask = 1U << (nr & 0x1f); in change_bit()
47 while (__bo_cas(a, old, old^mask) != old); in change_bit()
52 unsigned mask, old; in test_and_set_bit() local
[all …]
/linux/fs/xfs/
H A Dxfs_health.c106 unsigned int mask) in xfs_fs_mark_sick() argument
108 ASSERT(!(mask & ~XFS_SICK_FS_ALL)); in xfs_fs_mark_sick()
109 trace_xfs_fs_mark_sick(mp, mask); in xfs_fs_mark_sick()
112 mp->m_fs_sick |= mask; in xfs_fs_mark_sick()
120 unsigned int mask) in xfs_fs_mark_corrupt() argument
122 ASSERT(!(mask & ~XFS_SICK_FS_ALL)); in xfs_fs_mark_corrupt()
123 trace_xfs_fs_mark_corrupt(mp, mask); in xfs_fs_mark_corrupt()
126 mp->m_fs_sick |= mask; in xfs_fs_mark_corrupt()
127 mp->m_fs_checked |= mask; in xfs_fs_mark_corrupt()
135 unsigned int mask) in xfs_fs_mark_healthy() argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dce80/
H A Dhw_translate_dce80.c48 uint32_t mask = 1; in index_from_vector() local
51 if (vector == mask) in index_from_vector()
55 mask <<= 1; in index_from_vector()
56 } while (mask); in index_from_vector()
65 uint32_t mask, in offset_to_id() argument
73 switch (mask) { in offset_to_id()
103 switch (mask) { in offset_to_id()
130 switch (mask) { in offset_to_id()
145 switch (mask) { in offset_to_id()
166 *en = index_from_vector(mask); in offset_to_id()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dce60/
H A Dhw_translate_dce60.c48 uint32_t mask = 1; in index_from_vector() local
51 if (vector == mask) in index_from_vector()
55 mask <<= 1; in index_from_vector()
56 } while (mask); in index_from_vector()
65 uint32_t mask, in offset_to_id() argument
73 switch (mask) { in offset_to_id()
103 switch (mask) { in offset_to_id()
130 switch (mask) { in offset_to_id()
145 switch (mask) { in offset_to_id()
166 *en = index_from_vector(mask); in offset_to_id()
[all …]
/linux/kernel/bpf/
H A Dtnum.c12 #define TNUM(_v, _m) (struct tnum){.value = _v, .mask = _m}
14 const struct tnum tnum_unknown = { .value = 0, .mask = -1 };
39 return TNUM(a.value << shift, a.mask << shift); in tnum_lshift()
44 return TNUM(a.value >> shift, a.mask >> shift); in tnum_rshift()
56 (u32)(((s32)a.mask) >> min_shift)); in tnum_arshift()
59 (s64)a.mask >> min_shift); in tnum_arshift()
66 sm = a.mask + b.mask; in tnum_add()
70 mu = chi | a.mask | b.mask; in tnum_add()
79 alpha = dv + a.mask; in tnum_sub()
80 beta = dv - b.mask; in tnum_sub()
[all …]
/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_vlan.c12 u32 mask[3]; in sparx5_vlant_set_mask() local
14 /* Divide up mask in 32 bit words */ in sparx5_vlant_set_mask()
15 bitmap_to_arr32(mask, sparx5->vlan_mask[vid], SPX5_PORTS); in sparx5_vlant_set_mask()
17 /* Output mask to respective registers */ in sparx5_vlant_set_mask()
18 spx5_wr(mask[0], sparx5, ANA_L3_VLAN_MASK_CFG(vid)); in sparx5_vlant_set_mask()
20 spx5_wr(mask[1], sparx5, ANA_L3_VLAN_MASK_CFG1(vid)); in sparx5_vlant_set_mask()
21 spx5_wr(mask[2], sparx5, ANA_L3_VLAN_MASK_CFG2(vid)); in sparx5_vlant_set_mask()
123 u32 val, mask; in sparx5_pgid_update_mask() local
125 /* mask is spread across 3 registers x 32 bit */ in sparx5_pgid_update_mask()
127 mask = BIT(port->portno); in sparx5_pgid_update_mask()
[all …]

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