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Searched full:mpidr_el1 (Results 1 – 16 of 16) sorted by relevance

/linux/arch/arm64/kernel/
H A Dsleep.S10 * Implementation of MPIDR_EL1 hash algorithm through shifting
18 * @mpidr: register containing MPIDR_EL1 value
79 mrs x7, mpidr_el1
120 mrs x1, mpidr_el1
H A Dhead.S340 mrs x2, mpidr_el1
/linux/arch/arm64/kvm/hyp/nvhe/
H A Dsysreg-sr.c33 __sysreg_restore_el1_state(ctxt, midr, ctxt_sys_reg(ctxt, MPIDR_EL1)); in __sysreg_restore_state_nvhe()
/linux/Documentation/devicetree/bindings/arm/
H A Dcpus.yaml65 MPIDR_EL1 register affinity bits.
70 MPIDR_EL1.
73 MPIDR_EL1.
77 The reg cell bits [23:0] must be set to bits [23:0] of MPIDR_EL1.
/linux/arch/arm64/include/asm/
H A Dcputype.h310 return read_cpuid(MPIDR_EL1); in read_cpuid_mpidr()
H A Dkvm_emulate.h506 return __vcpu_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK; in kvm_vcpu_get_mpidr_aff()
H A Dsysreg.h984 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
/linux/tools/arch/arm64/include/asm/
H A Dcputype.h296 return read_cpuid(MPIDR_EL1); in read_cpuid_mpidr()
H A Dsysreg.h983 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
/linux/drivers/perf/hisilicon/
H A Dhisi_uncore_sllc_pmu.c339 * while SCCL_ID is from MPIDR_EL1 by CPU. in hisi_sllc_pmu_init_data()
H A Dhisi_uncore_pmu.c441 * determined from the MPIDR_EL1, but the encoding varies by CPU:
/linux/tools/testing/selftests/kvm/arm64/
H A Dvgic_init.c832 /* Assume MPIDR_EL1.Aff*=0 */ in test_sysreg_array()
H A Dget-reg-list.c424 ARM64_SYS_REG(3, 0, 0, 0, 5), /* MPIDR_EL1 */
/linux/Documentation/arch/arm64/
H A Dcpu-feature-registers.rst410 get_cpu_ftr(MPIDR_EL1);
/linux/arch/arm64/tools/
H A Dsysreg3892 Field 26 MPIDR_EL1
/linux/arch/arm64/kvm/
H A Dsys_regs.c770 vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1); in reset_mpidr()
2880 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },