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/linux/drivers/pinctrl/qcom/
H A DKconfig51 tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver"
59 Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
63 tristate "Qualcomm Technologies Inc SC7280 LPASS LPI pin controller driver"
68 Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
72 tristate "Qualcomm Technologies Inc SM4250 LPASS LPI pin controller driver"
77 Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
81 tristate "Qualcomm Technologies Inc SM6115 LPASS LPI pin controller driver"
86 Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
90 tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver"
95 Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
[all …]
H A Dpinctrl-sc7280-lpass-lpi.c11 #include "pinctrl-lpass-lpi.h"
132 .compatible = "qcom,sc7280-lpass-lpi-pinctrl",
141 .name = "qcom-sc7280-lpass-lpi-pinctrl",
149 MODULE_DESCRIPTION("QTI SC7280 LPI GPIO pin control driver");
H A Dpinctrl-sm8250-lpass-lpi.c11 #include "pinctrl-lpass-lpi.h"
130 .compatible = "qcom,sm8250-lpass-lpi-pinctrl",
139 .name = "qcom-sm8250-lpass-lpi-pinctrl",
147 MODULE_DESCRIPTION("QTI SM8250 LPI GPIO pin control driver");
H A Dpinctrl-sm6115-lpass-lpi.c11 #include "pinctrl-lpass-lpi.h"
139 { .compatible = "qcom,sm6115-lpass-lpi-pinctrl", .data = &sm6115_lpi_data },
146 .name = "qcom-sm6115-lpass-lpi-pinctrl",
154 MODULE_DESCRIPTION("QTI SM6115 LPI GPIO pin control driver");
H A Dpinctrl-sm8350-lpass-lpi.c11 #include "pinctrl-lpass-lpi.h"
132 .compatible = "qcom,sm8350-lpass-lpi-pinctrl",
141 .name = "qcom-sm8350-lpass-lpi-pinctrl",
150 MODULE_DESCRIPTION("QTI SM8350 LPI GPIO pin control driver");
H A Dpinctrl-sm8450-lpass-lpi.c10 #include "pinctrl-lpass-lpi.h"
198 .compatible = "qcom,sm8450-lpass-lpi-pinctrl",
207 .name = "qcom-sm8450-lpass-lpi-pinctrl",
215 MODULE_DESCRIPTION("QTI SM8450 LPI GPIO pin control driver");
H A Dpinctrl-sm8550-lpass-lpi.c10 #include "pinctrl-lpass-lpi.h"
206 .compatible = "qcom,sm8550-lpass-lpi-pinctrl",
215 .name = "qcom-sm8550-lpass-lpi-pinctrl",
223 MODULE_DESCRIPTION("Qualcomm SM8550 LPI GPIO pin control driver");
H A Dpinctrl-sm8650-lpass-lpi.c10 #include "pinctrl-lpass-lpi.h"
213 .compatible = "qcom,sm8650-lpass-lpi-pinctrl",
222 .name = "qcom-sm8650-lpass-lpi-pinctrl",
230 MODULE_DESCRIPTION("Qualcomm SM8650 LPI GPIO pin control driver");
/linux/drivers/acpi/riscv/
H A Dcpuidle.c25 struct acpi_lpi_state *lpi; in acpi_cpu_init_idle() local
40 lpi = &pr->power.lpi_states[i]; in acpi_cpu_init_idle()
48 if (((lpi->address & RISCV_FFH_LPI_TYPE_MASK) != RISCV_FFH_LPI_TYPE_SBI) || in acpi_cpu_init_idle()
49 (lpi->address & RISCV_FFH_LPI_RSVD_MASK)) { in acpi_cpu_init_idle()
50 pr_warn("Invalid LPI entry method %#llx\n", lpi->address); in acpi_cpu_init_idle()
54 state = lpi->address; in acpi_cpu_init_idle()
69 int acpi_processor_ffh_lpi_enter(struct acpi_lpi_state *lpi) in acpi_processor_ffh_lpi_enter() argument
71 u32 state = lpi->address; in acpi_processor_ffh_lpi_enter()
75 lpi->index, in acpi_processor_ffh_lpi_enter()
79 lpi->index, in acpi_processor_ffh_lpi_enter()
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,sm8550-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM8550 SoC LPASS LPI TLMM
15 (LPASS) Low Power Island (LPI) of Qualcomm SM8550 SoC.
20 - const: qcom,sm8550-lpass-lpi-pinctrl
22 - const: qcom,x1e80100-lpass-lpi-pinctrl
23 - const: qcom,sm8550-lpass-lpi-pinctrl
27 - description: LPASS LPI TLMM Control and Status registers
28 - description: LPASS LPI MCC registers
55 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
80 - $ref: qcom,lpass-lpi-common.yaml#
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H A Dqcom,sm6115-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM6115 SoC LPASS LPI TLMM
15 (LPASS) Low Power Island (LPI) of Qualcomm SM6115 SoC.
19 const: qcom,sm6115-lpass-lpi-pinctrl
23 - description: LPASS LPI TLMM Control and Status registers
24 - description: LPASS LPI MCC registers
49 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
71 - $ref: qcom,lpass-lpi-common.yaml#
86 compatible = "qcom,sm6115-lpass-lpi-pinctrl";
H A Dqcom,sm4250-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM4250 SoC LPASS LPI TLMM
14 (LPASS) Low Power Island (LPI) of Qualcomm SM4250 SoC.
18 const: qcom,sm4250-lpass-lpi-pinctrl
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
48 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
72 - $ref: qcom,lpass-lpi-common.yaml#
86 compatible = "qcom,sm4250-lpass-lpi-pinctrl";
H A Dqcom,sm8450-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM8450 SoC LPASS LPI TLMM
14 (LPASS) Low Power Island (LPI) of Qualcomm SM8450 SoC.
18 const: qcom,sm8450-lpass-lpi-pinctrl
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
50 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
76 - $ref: qcom,lpass-lpi-common.yaml#
90 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
H A Dqcom,sc7280-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SC7280 SoC LPASS LPI TLMM
14 (LPASS) Low Power Island (LPI) of Qualcomm SC7280 SoC.
18 const: qcom,sc7280-lpass-lpi-pinctrl
38 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
67 - $ref: qcom,lpass-lpi-common.yaml#
74 compatible = "qcom,sc7280-lpass-lpi-pinctrl";
H A Dqcom,sm8250-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM8250 SoC LPASS LPI TLMM
14 (LPASS) Low Power Island (LPI) of Qualcomm SM8250 SoC.
18 const: qcom,sm8250-lpass-lpi-pinctrl
48 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
73 - $ref: qcom,lpass-lpi-common.yaml#
87 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
H A Dqcom,lpass-lpi-common.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-common.yaml#
7 title: Qualcomm SoC LPASS LPI TLMM Common Properties
16 Low Power Audio SubSystem (LPASS) Low Power Island (LPI) of Qualcomm SoCs.
/linux/drivers/acpi/arm64/
H A Dcpuidle.c20 struct acpi_lpi_state *lpi; in psci_acpi_cpu_init_idle() local
40 lpi = &pr->power.lpi_states[i + 1]; in psci_acpi_cpu_init_idle()
45 state = lpi->address; in psci_acpi_cpu_init_idle()
60 __cpuidle int acpi_processor_ffh_lpi_enter(struct acpi_lpi_state *lpi) in acpi_processor_ffh_lpi_enter() argument
62 u32 state = lpi->address; in acpi_processor_ffh_lpi_enter()
64 if (ARM64_LPI_IS_RETENTION_STATE(lpi->arch_flags)) in acpi_processor_ffh_lpi_enter()
66 lpi->index, state); in acpi_processor_ffh_lpi_enter()
69 lpi->index, state); in acpi_processor_ffh_lpi_enter()
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Dcommon.h384 /* EEE and LPI defines */
517 /* Default LPI timers */
522 /* Common LPI register bits */
523 #define LPI_CTRL_STATUS_LPITCSE BIT(21) /* LPI Tx Clock Stop Enable, gmac4, xgmac2 only */
524 #define LPI_CTRL_STATUS_LPIATE BIT(20) /* LPI Timer Enable, gmac4 only */
525 #define LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */
528 #define LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */
529 #define LPI_CTRL_STATUS_RLPIST BIT(9) /* Receive LPI state, gmac1000 only? */
530 #define LPI_CTRL_STATUS_TLPIST BIT(8) /* Transmit LPI state, gmac1000 only? */
531 #define LPI_CTRL_STATUS_RLPIEX BIT(3) /* Receive LPI Exit */
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/linux/drivers/irqchip/
H A Dirq-gic-v5.c56 static void release_lpi(u32 lpi) in release_lpi() argument
58 ida_free(&lpi_ida, lpi); in release_lpi()
66 void gicv5_free_lpi(u32 lpi) in gicv5_free_lpi() argument
68 release_lpi(lpi); in gicv5_free_lpi()
197 * unmasking an SPI/LPI IRQ. in gicv5_iri_irq_unmask()
502 /* Mark the LPI pending */ in gicv5_ipi_send_single()
551 .name = "GICv5-LPI",
743 * state to make sure we start the LPI with a clean state from in gicv5_lpi_config_reset()
759 u32 *lpi = arg; in gicv5_irq_lpi_domain_alloc() local
765 hwirq = *lpi; in gicv5_irq_lpi_domain_alloc()
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/linux/drivers/acpi/
H A Dprocessor_idle.c934 /* LPI States start at index 3 */ in acpi_processor_evaluate_lpi()
1002 * flat_state_cnt - the number of composite LPI states after the process of flattening
1007 * combine_lpi_states - combine local and parent LPI states to form a composite LPI state
1009 * @local: local LPI state
1010 * @parent: parent LPI state
1011 * @result: composite LPI state
1063 pr_warn("Limiting number of LPI states to max (%d)\n", in flatten_lpi_states()
1145 /* flatten all the LPI states in this level of hierarchy */ in acpi_processor_get_lpi_info()
1165 int __weak acpi_processor_ffh_lpi_enter(struct acpi_lpi_state *lpi) in acpi_processor_ffh_lpi_enter() argument
1171 * acpi_idle_lpi_enter - enters an ACPI any LPI state
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/linux/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_core.c53 /* Reading this register shall clear all the LPI status bits */ in sxgbe_get_lpi_status()
190 /* Enable the LPI mode for transmit path with Tx automate bit set. in sxgbe_set_eee_mode()
192 * to LPI mode after all outstanding and pending packets are in sxgbe_set_eee_mode()
229 /* Program the timers in the LPI timer control register: in sxgbe_set_eee_timer()
232 * the LPI pattern. in sxgbe_set_eee_timer()
234 * after it has stopped transmitting the LPI pattern. in sxgbe_set_eee_timer()
H A Dsxgbe_common.h118 /* EEE-LPI mode flags*/
124 /* EEE-LPI Interrupt status flag */
127 /* EEE-LPI Default timer values */
131 /* EEE-LPI Control and status definitions */
243 /* EEE-LPI stats */
348 /* EEE-LPI specific operations */
501 /* EEE-LPI specific members */
/linux/arch/arm64/boot/dts/qcom/
H A Dsm4250.dtsi41 compatible = "qcom,sm4250-lpass-lpi-pinctrl";
44 lpi_i2s2_active: lpi-i2s2-active-state {
/linux/drivers/acpi/x86/
H A Ds2idle.c135 "LPI: constraints list begin:\n"); in lpi_device_get_constraints_amd()
186 acpi_handle_debug(lps0_device_handle, "LPI: constraints list end\n"); in lpi_device_get_constraints_amd()
213 acpi_handle_debug(lps0_device_handle, "LPI: constraints list begin:\n"); in lpi_device_get_constraints()
296 acpi_handle_debug(lps0_device_handle, "LPI: constraints list end\n"); in lpi_device_get_constraints()
337 "LPI: required min power state:%s current power state:%s\n", in lpi_check_constraints()
342 acpi_handle_info(entry->handle, "LPI: Device not power manageable\n"); in lpi_check_constraints()
349 "LPI: Constraint not met; min power state:%s current power state:%s\n", in lpi_check_constraints()
/linux/Documentation/devicetree/bindings/net/
H A Dsnps,dwc-qos-ethernet.txt108 - snps,en-lpi: If present it enables use of the AXI low-power interface
117 - snps,en-tx-lpi-clockgating: Enable gating of the MAC TX clock during
149 snps,en-tx-lpi-clockgating;
150 snps,en-lpi;

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