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/linux/Documentation/devicetree/bindings/clock/ !
H A Dqcom,mmcc.yaml97 - description: MMSS GPLL0 voted clock
98 - description: GPLL0 voted clock
125 - description: MMSS GPLL0 voted clock
126 - description: GPLL0 voted clock
164 - description: MMSS GPLL0 voted clock
165 - description: GPLL0 clock
166 - description: GPLL0 voted clock
181 - const: gpll0
228 - const: gpll0
258 - const: gpll0
[all …]
H A Dqcom,qcs615-gpucc.yaml25 - description: GPLL0 main branch source
26 - description: GPLL0 GPUCC div branch source
42 <&gcc GPLL0>,
H A Dqcom,msm8998-gpucc.yaml25 - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src)
30 - const: gpll0
54 clock-names = "xo", "gpll0";
H A Dqcom,sm6115-gpucc.yaml26 - description: GPLL0 main branch source
27 - description: GPLL0 main div source
H A Dqcom,gpucc-sdm660.yaml27 - description: GPLL0 main gpu branch
28 - description: GPLL0 divider gpu branch
H A Dqcom,qcm2290-dispcc.yaml26 - description: GPLL0 source from GCC
27 - description: GPLL0 div source from GCC
H A Dqcom,qcm2290-gpucc.yaml30 - description: GPLL0 main branch source
31 - description: GPLL0 div branch source
H A Dqcom,sm6375-gpucc.yaml26 - description: GPLL0 main branch source
27 - description: GPLL0 div branch source
H A Dqcom,sm8450-gpucc.yaml42 - description: GPLL0 main branch source
43 - description: GPLL0 div branch source
H A Dqcom,gpucc.yaml47 - description: GPLL0 main branch source
48 - description: GPLL0 div branch source
H A Dqcom,sm6375-dispcc.yaml28 - description: GPLL0 source from GCC
H A Dqcom,sm6125-gpucc.yaml26 - description: GPLL0 main branch source
/linux/Documentation/devicetree/bindings/remoteproc/ !
H A Dqcom,msm8996-mss-pil.yaml220 - description: GCC MSS GPLL0 clock
255 - description: GCC MSS GPLL0 clock
292 - description: GCC MSS GPLL0 clock
/linux/drivers/clk/qcom/ !
H A Dgcc-qcs615.c44 static struct clk_alpha_pll gpll0 = { variable
51 .name = "gpll0",
61 /* Fixed divider clock of GPLL0 instead of PLL normal postdiv */
68 .hw = &gpll0.clkr.hw,
226 { .hw = &gpll0.clkr.hw },
232 { .hw = &gpll0.clkr.hw },
233 { .hw = &gpll0.clkr.hw },
245 { .hw = &gpll0.clkr.hw },
259 { .hw = &gpll0.clkr.hw },
292 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-sm6115.c57 static struct clk_alpha_pll gpll0 = { variable
66 .name = "gpll0",
90 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
110 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
475 { .hw = &gpll0.clkr.hw },
488 { .hw = &gpll0.clkr.hw },
502 { .hw = &gpll0.clkr.hw },
517 { .hw = &gpll0.clkr.hw },
532 { .hw = &gpll0.clkr.hw },
548 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-sm6375.c61 static struct clk_alpha_pll gpll0 = { variable
68 .name = "gpll0",
93 &gpll0.clkr.hw,
115 &gpll0.clkr.hw,
447 { .hw = &gpll0.clkr.hw },
460 { .hw = &gpll0.clkr.hw },
474 { .hw = &gpll0.clkr.hw },
481 { .hw = &gpll0.clkr.hw },
497 { .hw = &gpll0.clkr.hw },
515 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-sm6350.c34 static struct clk_alpha_pll gpll0 = { variable
41 .name = "gpll0",
66 &gpll0.clkr.hw,
88 &gpll0.clkr.hw,
160 { .hw = &gpll0.clkr.hw },
201 { .hw = &gpll0.clkr.hw },
260 &gpll0.clkr.hw,
274 &gpll0.clkr.hw,
1163 &gpll0.clkr.hw,
1277 &gpll0.clkr.hw,
[all …]
H A Dgcc-ipq9574.c97 static struct clk_alpha_pll_postdiv gpll0 = { variable
102 .name = "gpll0",
200 { .hw = &gpll0.clkr.hw },
212 { .hw = &gpll0.clkr.hw },
222 { .hw = &gpll0.clkr.hw },
234 { .hw = &gpll0.clkr.hw },
236 { .hw = &gpll0.clkr.hw },
248 { .hw = &gpll0.clkr.hw },
262 { .hw = &gpll0.clkr.hw },
274 { .hw = &gpll0.clkr.hw },
[all …]
H A Dmmcc-msm8996.c51 { .fw_name = "gpll0", .name = "gpll0" },
353 { .fw_name = "gpll0", .name = "gpll0" },
379 { .fw_name = "gpll0", .name = "gpll0" },
395 { .fw_name = "gpll0", .name = "gpll0" },
411 { .fw_name = "gpll0", .name = "gpll0" },
427 { .fw_name = "gpll0", .name = "gpll0" },
443 { .fw_name = "gpll0", .name = "gpll0" },
462 { .fw_name = "gpll0", .name = "gpll0" },
481 { .fw_name = "gpll0", .name = "gpll0" },
501 { .fw_name = "gpll0", .name = "gpll0" },
H A Dgcc-msm8953.c69 static struct clk_alpha_pll_postdiv gpll0 = { variable
73 .name = "gpll0",
243 { .hw = &gpll0.clkr.hw },
255 { .hw = &gpll0.clkr.hw },
678 { .hw = &gpll0.clkr.hw },
748 { .hw = &gpll0.clkr.hw },
783 { .hw = &gpll0.clkr.hw },
849 { .hw = &gpll0.clkr.hw },
912 { .hw = &gpll0.clkr.hw },
1019 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-sdm845.c37 static struct clk_alpha_pll gpll0 = { variable
44 .name = "gpll0",
106 &gpll0.clkr.hw,
121 { .hw = &gpll0.clkr.hw },
134 { .hw = &gpll0.clkr.hw },
156 { .hw = &gpll0.clkr.hw },
176 { .hw = &gpll0.clkr.hw },
183 { .hw = &gpll0.clkr.hw },
190 { .hw = &gpll0.clkr.hw },
196 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-ipq5018.c121 static struct clk_alpha_pll_postdiv gpll0 = { variable
126 .name = "gpll0",
194 { .hw = &gpll0.clkr.hw },
206 { .hw = &gpll0.clkr.hw },
217 { .hw = &gpll0.clkr.hw },
229 { .hw = &gpll0.clkr.hw },
240 { .hw = &gpll0.clkr.hw },
252 { .hw = &gpll0.clkr.hw },
266 { .hw = &gpll0.clkr.hw },
278 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-ipq5332.c79 static struct clk_alpha_pll_postdiv gpll0 = { variable
84 .name = "gpll0",
160 { .hw = &gpll0.clkr.hw },
171 { .hw = &gpll0.clkr.hw },
182 { .hw = &gpll0.clkr.hw },
195 { .hw = &gpll0.clkr.hw },
210 { .hw = &gpll0.clkr.hw },
223 { .hw = &gpll0.clkr.hw },
224 { .hw = &gpll0.clkr.hw },
238 { .hw = &gpll0.clkr.hw },
[all …]
H A Dgcc-sdx65.c35 static struct clk_alpha_pll gpll0 = { variable
42 .name = "gpll0",
66 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
80 { .hw = &gpll0.clkr.hw },
86 { .hw = &gpll0.clkr.hw },
99 { .hw = &gpll0.clkr.hw },
1511 [GPLL0] = &gpll0.clkr,
/linux/Documentation/devicetree/bindings/mailbox/ !
H A Dqcom,apcs-kpss-global.yaml173 - description: GCC GPLL0 clock source
178 - const: gpll0

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