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/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A Dpipeline.json9 …tion": "This event is deprecated. Refer to new event ARITH.DIV_ACTIVE Available PDIST counters: 0",
19 … root operations. Accounts for integer and floating-point operations. Available PDIST counters: 0",
30 …on": "This event is deprecated. Refer to new event ARITH.FPDIV_ACTIVE Available PDIST counters: 0",
40 …cription": "This event counts the cycles the integer divider is busy. Available PDIST counters: 0",
51 …ion": "This event is deprecated. Refer to new event ARITH.IDIV_ACTIVE Available PDIST counters: 0",
60 … Examples include AD (page Access Dirty), FP and AVX related assists. Available PDIST counters: 0",
69 "PublicDescription": "Counts all branch instructions retired. Available PDIST counters: 0",
77 …"PublicDescription": "Counts conditional branch instructions retired. Available PDIST counters: 0",
86 … "PublicDescription": "Counts not taken branch instructions retired. Available PDIST counters: 0",
95 …cDescription": "Counts taken conditional branch instructions retired. Available PDIST counters: 0",
[all …]
H A Dcache.json7 "PublicDescription": "L1D.HWPF_MISS Available PDIST counters: 0",
16 …and replacements that require stall-for-replace or block-for-replace. Available PDIST counters: 0",
25 …cheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: 0",
36 …cheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: 0",
46 …"This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS Available PDIST counters: 0",
55 …cheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: 0",
64 …ne splits and reads due to page walks resulted from any request type. Available PDIST counters: 0",
74 …blicDescription": "Counts duration of L1D miss outstanding in cycles. Available PDIST counters: 0",
83 …er of L2 cache lines filling the L2. Counting does not cover rejects. Available PDIST counters: 0",
92 …se lines are in Modified state. Modified lines are written back to L3 Available PDIST counters: 0",
[all …]
H A Dfrontend.json7 …he branch is not tracked by the BPU (Branch Prediction Unit) anymore. Available PDIST counters: 0",
16 …cle penalty for each LCP (Length changing prefix) in a 16-byte chunk. Available PDIST counters: 0",
25 "PublicDescription": "Cycles the Microcode Sequencer is busy. Available PDIST counters: 0",
34 …ounts fetch penalty cycles when a transition occurs from DSB to MITE. Available PDIST counters: 0",
45 …d DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Available PDIST counters: 0",
56 …eans stalls were exposed to the back-end as a result of the DSB miss. Available PDIST counters: 0",
67 …tired Instructions that experienced iTLB (Instruction TLB) true miss. Available PDIST counters: 0",
78 … retired Instructions who experienced Instruction L1 Cache true miss. Available PDIST counters: 0",
89 … retired Instructions who experienced Instruction L2 Cache true miss. Available PDIST counters: 0",
100 …od of at least 1 cycle which was not interrupted by a back-end stall. Available PDIST counters: 0",
[all …]
H A Dvirtual-memory.json7 …ds that miss the DTLB (Data TLB) and hit the STLB (Second level TLB). Available PDIST counters: 0",
17 …e PMH (Page Miss Handler) is busy with a page walk for a demand load. Available PDIST counters: 0",
26 …further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
35 …further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
44 …further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
53 …further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
62 …standing for a demand load in the PMH (Page Miss Handler) each cycle. Available PDIST counters: 0",
71 …tores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB). Available PDIST counters: 0",
81 …ast one PMH (Page Miss Handler) is busy with a page walk for a store. Available PDIST counters: 0",
90 …further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
[all …]
/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A Dpipeline.json9 …tion": "This event is deprecated. Refer to new event ARITH.DIV_ACTIVE Available PDIST counters: 0",
19 … root operations. Accounts for integer and floating-point operations. Available PDIST counters: 0",
30 …on": "This event is deprecated. Refer to new event ARITH.FPDIV_ACTIVE Available PDIST counters: 0",
40 …cription": "This event counts the cycles the integer divider is busy. Available PDIST counters: 0",
51 …ion": "This event is deprecated. Refer to new event ARITH.IDIV_ACTIVE Available PDIST counters: 0",
60 … Examples include AD (page Access Dirty), FP and AVX related assists. Available PDIST counters: 0",
69 "PublicDescription": "Counts all branch instructions retired. Available PDIST counters: 0",
77 …"PublicDescription": "Counts conditional branch instructions retired. Available PDIST counters: 0",
86 … "PublicDescription": "Counts not taken branch instructions retired. Available PDIST counters: 0",
95 …cDescription": "Counts taken conditional branch instructions retired. Available PDIST counters: 0",
[all …]
H A Dcache.json7 "PublicDescription": "L1D.HWPF_MISS Available PDIST counters: 0",
16 …and replacements that require stall-for-replace or block-for-replace. Available PDIST counters: 0",
25 …cheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: 0",
36 …cheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: 0",
46 …"This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS Available PDIST counters: 0",
55 …cheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: 0",
64 …ne splits and reads due to page walks resulted from any request type. Available PDIST counters: 0",
74 …blicDescription": "Counts duration of L1D miss outstanding in cycles. Available PDIST counters: 0",
83 …er of L2 cache lines filling the L2. Counting does not cover rejects. Available PDIST counters: 0",
92 …se lines are in Modified state. Modified lines are written back to L3 Available PDIST counters: 0",
[all …]
H A Dfrontend.json7 …he branch is not tracked by the BPU (Branch Prediction Unit) anymore. Available PDIST counters: 0",
16 …cle penalty for each LCP (Length changing prefix) in a 16-byte chunk. Available PDIST counters: 0",
25 "PublicDescription": "Cycles the Microcode Sequencer is busy. Available PDIST counters: 0",
34 …ounts fetch penalty cycles when a transition occurs from DSB to MITE. Available PDIST counters: 0",
45 …d DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Available PDIST counters: 0",
56 …eans stalls were exposed to the back-end as a result of the DSB miss. Available PDIST counters: 0",
67 …tired Instructions that experienced iTLB (Instruction TLB) true miss. Available PDIST counters: 0",
78 … retired Instructions who experienced Instruction L1 Cache true miss. Available PDIST counters: 0",
89 … retired Instructions who experienced Instruction L2 Cache true miss. Available PDIST counters: 0",
100 …od of at least 1 cycle which was not interrupted by a back-end stall. Available PDIST counters: 0",
[all …]
H A Dvirtual-memory.json7 …ds that miss the DTLB (Data TLB) and hit the STLB (Second level TLB). Available PDIST counters: 0",
17 …e PMH (Page Miss Handler) is busy with a page walk for a demand load. Available PDIST counters: 0",
26 …further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
35 …further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
44 …further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
53 …further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
62 …standing for a demand load in the PMH (Page Miss Handler) each cycle. Available PDIST counters: 0",
71 …tores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB). Available PDIST counters: 0",
81 …ast one PMH (Page Miss Handler) is busy with a page walk for a store. Available PDIST counters: 0",
90 …further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
[all …]
/linux/drivers/infiniband/core/
H A Duverbs_std_types_counters.c42 struct ib_counters *counters = uobject->object; in uverbs_free_counters() local
45 if (atomic_read(&counters->usecnt)) in uverbs_free_counters()
48 ret = counters->device->ops.destroy_counters(counters); in uverbs_free_counters()
51 kfree(counters); in uverbs_free_counters()
61 struct ib_counters *counters; in UVERBS_HANDLER() local
72 counters = rdma_zalloc_drv_obj(ib_dev, ib_counters); in UVERBS_HANDLER()
73 if (!counters) in UVERBS_HANDLER()
76 counters->device = ib_dev; in UVERBS_HANDLER()
77 counters->uobject = uobj; in UVERBS_HANDLER()
78 uobj->object = counters; in UVERBS_HANDLER()
[all …]
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A Dpipeline.json8 … root operations. Accounts for integer and floating-point operations. Available PDIST counters: 0",
18 …cription": "This event counts the cycles the integer divider is busy. Available PDIST counters: 0",
27 … Examples include AD (page Access Dirty), FP and AVX related assists. Available PDIST counters: 0",
36 "PublicDescription": "Counts all branch instructions retired. Available PDIST counters: 0",
44 …"PublicDescription": "Counts conditional branch instructions retired. Available PDIST counters: 0",
53 … "PublicDescription": "Counts not taken branch instructions retired. Available PDIST counters: 0",
62 …cDescription": "Counts taken conditional branch instructions retired. Available PDIST counters: 0",
71 "PublicDescription": "Counts far branch instructions retired. Available PDIST counters: 0",
80 …tructions retired excluding returns. TSX abort is an indirect branch. Available PDIST counters: 0",
89 …on": "Counts both direct and indirect near call instructions retired. Available PDIST counters: 0",
[all …]
H A Dfrontend.json7 …he branch is not tracked by the BPU (Branch Prediction Unit) anymore. Available PDIST counters: 0",
16 …cle penalty for each LCP (Length changing prefix) in a 16-byte chunk. Available PDIST counters: 0",
25 "PublicDescription": "Cycles the Microcode Sequencer is busy. Available PDIST counters: 0",
34 …ounts fetch penalty cycles when a transition occurs from DSB to MITE. Available PDIST counters: 0",
45 …ANT) conditional retired branches (no BTB entry and not mispredicted) Available PDIST counters: 0",
56 …d DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Available PDIST counters: 0",
70 …eans stalls were exposed to the back-end as a result of the DSB miss. Available PDIST counters: 0",
81 …tired Instructions that experienced iTLB (Instruction TLB) true miss. Available PDIST counters: 0",
95 … retired Instructions who experienced Instruction L1 Cache true miss. Available PDIST counters: 0",
109 … retired Instructions who experienced Instruction L2 Cache true miss. Available PDIST counters: 0",
[all …]
H A Dvirtual-memory.json7 …ds that miss the DTLB (Data TLB) and hit the STLB (Second level TLB). Available PDIST counters: 0",
17 …e PMH (Page Miss Handler) is busy with a page walk for a demand load. Available PDIST counters: 0",
26 …further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
35 …further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
44 …further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
53 …further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
62 …standing for a demand load in the PMH (Page Miss Handler) each cycle. Available PDIST counters: 0",
71 …tores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB). Available PDIST counters: 0",
81 …ast one PMH (Page Miss Handler) is busy with a page walk for a store. Available PDIST counters: 0",
90 …further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
[all …]
/linux/net/netfilter/
H A Dxt_connbytes.c30 const struct nf_conn_counter *counters; in connbytes_mt() local
40 counters = acct->counter; in connbytes_mt()
45 what = atomic64_read(&counters[IP_CT_DIR_ORIGINAL].packets); in connbytes_mt()
48 what = atomic64_read(&counters[IP_CT_DIR_REPLY].packets); in connbytes_mt()
51 what = atomic64_read(&counters[IP_CT_DIR_ORIGINAL].packets); in connbytes_mt()
52 what += atomic64_read(&counters[IP_CT_DIR_REPLY].packets); in connbytes_mt()
59 what = atomic64_read(&counters[IP_CT_DIR_ORIGINAL].bytes); in connbytes_mt()
62 what = atomic64_read(&counters[IP_CT_DIR_REPLY].bytes); in connbytes_mt()
65 what = atomic64_read(&counters[IP_CT_DIR_ORIGINAL].bytes); in connbytes_mt()
66 what += atomic64_read(&counters[IP_CT_DIR_REPLY].bytes); in connbytes_mt()
[all …]
/linux/lib/
H A Dpercpu_counter.c3 * Fast batching percpu counters.
67 s32 *pcount = per_cpu_ptr(fbc->counters, cpu); in percpu_counter_set()
83 * the this_cpu_add(), and the interrupt updates this_cpu(*fbc->counters),
98 count = this_cpu_read(*fbc->counters); in percpu_counter_add_batch()
106 count = __this_cpu_read(*fbc->counters); in percpu_counter_add_batch()
108 __this_cpu_sub(*fbc->counters, count); in percpu_counter_add_batch()
112 } while (!this_cpu_try_cmpxchg(*fbc->counters, &count, count + amount)); in percpu_counter_add_batch()
126 count = __this_cpu_read(*fbc->counters) + amount; in percpu_counter_add_batch()
130 __this_cpu_sub(*fbc->counters, count - amount); in percpu_counter_add_batch()
133 this_cpu_add(*fbc->counters, amount); in percpu_counter_add_batch()
[all …]
/linux/tools/testing/selftests/net/tcp_ao/lib/
H A Dproc.c18 struct netstat_counter *counters; member
52 ret->counters = NULL; in lookup_get()
81 type->counters = reallocarray(type->counters, in netstat_read_type()
84 if (!type->counters) in netstat_read_type()
95 struct netstat_counter *nc = &type->counters[i]; in netstat_read_type()
133 type->counters = reallocarray(type->counters, i + 1, in snmp6_read()
135 if (!type->counters) in snmp6_read()
137 nc = &type->counters[i]; in snmp6_read()
196 free(ns->counters[i].name); in netstat_free()
197 free(ns->counters); in netstat_free()
[all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Dmemory.json16 …: "Counts the number of misaligned load uops that are 4K page splits. Available PDIST counters: 0",
26 … "Counts the number of misaligned store uops that are 4K page splits. Available PDIST counters: 0",
37 …ublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: 0",
48 …tion": "Counts all code reads that were not supplied by the L3 cache. Available PDIST counters: 0",
59 …tion": "Counts all code reads that were not supplied by the L3 cache. Available PDIST counters: 0",
70 …ublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: 0",
81 …ks from L1 cache and L2 cache that were not supplied by the L3 cache. Available PDIST counters: 0",
92 …ks from L1 cache and L2 cache that were not supplied by the L3 cache. Available PDIST counters: 0",
103 …tches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST counters: 0",
114 … instruction cache prefetches that were not supplied by the L3 cache. Available PDIST counters: 0",
[all …]
H A Dcache.json164 …scription": "Counts the number of load uops retired that hit in DRAM. Available PDIST counters: 0",
175 …required and modified data was forwarded from another core or module. Available PDIST counters: 0",
186 …Counts the number of load uops retired that hit in the L1 data cache. Available PDIST counters: 0",
197 …ounts the number of load uops retired that miss in the L1 data cache. Available PDIST counters: 0",
208 …n": "Counts the number of load uops retired that hit in the L2 cache. Available PDIST counters: 0",
219 …": "Counts the number of load uops retired that miss in the L2 cache. Available PDIST counters: 0",
230 …n": "Counts the number of load uops retired that hit in the L3 cache. Available PDIST counters: 0",
241 … load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST) Available PDIST counters: 0",
252 … "PublicDescription": "Counts the total number of load uops retired. Available PDIST counters: 0",
263 … "PublicDescription": "Counts the total number of store uops retired. Available PDIST counters: 0",
[all …]
/linux/tools/perf/
H A Ddesign.txt2 Performance Counters for Linux
5 Performance counters are special hardware registers available on most modern
13 hardware capabilities. It provides per task and per CPU counters, counter
15 provides "virtual" 64-bit counters, regardless of the width of the
16 underlying hardware counters.
18 Performance counters are accessed via special file descriptors.
32 Multiple counters can be kept open at a time, and the counters
115 on all CPUs that implement Performance Counters support under Linux,
130 * Special "software" counters provided by the kernel, even if the hardware
131 * does not support performance counters. These counters measure various
[all …]
/linux/Documentation/arch/arm64/
H A Damu.rst22 counters intended for system management use. The AMU extension provides a
27 of four fixed and architecturally defined 64-bit event counters.
37 When in WFI or WFE these counters do not increment.
40 event counters. Future versions of the architecture may use this space to
41 implement additional architected event counters.
44 64-bit event counters.
46 On cold reset all counters reset to 0.
59 counters, only the presence of the extension.
66 - Enable the counters. If not enabled these will read as 0.
67 - Save/restore the counters before/after the CPU is being put/brought up
[all …]
/linux/Documentation/core-api/
H A Dlocal_ops.rst30 counters. They minimize the performance cost of standard atomic operations by
34 Having fast per CPU atomic counters is interesting in many cases: it does not
36 coherent counters in NMI handlers. It is especially useful for tracing purposes
37 and for various performance monitoring counters.
95 static DEFINE_PER_CPU(local_t, counters) = LOCAL_INIT(0);
107 local_inc(&get_cpu_var(counters));
108 put_cpu_var(counters);
113 local_inc(this_cpu_ptr(&counters));
117 Reading the counters
120 Those local counters can be read from foreign CPUs to sum the count. Note that
[all …]
/linux/Documentation/translations/zh_CN/core-api/
H A Dlocal_ops.rst93 static DEFINE_PER_CPU(local_t, counters) = LOCAL_INIT(0);
105 local_inc(&get_cpu_var(counters));
106 put_cpu_var(counters);
110 local_inc(this_cpu_ptr(&counters));
123 sum += local_read(&per_cpu(counters, cpu));
143 static DEFINE_PER_CPU(local_t, counters) = LOCAL_INIT(0);
152 local_inc(this_cpu_ptr(&counters));
157 * local_inc(&get_cpu_var(counters));
158 * put_cpu_var(counters);
166 /* Increment the counters */
[all …]
/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A Dcache.json17 "PublicDescription": "L1D.HWPF_MISS Available PDIST counters: 0",
27 …and replacements that require stall-for-replace or block-for-replace. Available PDIST counters: 0",
37 …cheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: 0",
49 …cheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: 0",
59 …cheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: 0",
69 …ne splits and reads due to page walks resulted from any request type. Available PDIST counters: 0",
80 …blicDescription": "Counts duration of L1D miss outstanding in cycles. Available PDIST counters: 0",
90 …er of L2 cache lines filling the L2. Counting does not cover rejects. Available PDIST counters: 0",
150 …se lines are in Modified state. Modified lines are written back to L3 Available PDIST counters: 0",
170 …nes are typically in Shared or Exclusive state. A non-threaded event. Available PDIST counters: 0",
[all …]
/linux/drivers/net/ethernet/aquantia/atlantic/macsec/
H A Dmacsec_api.h265 /*! Read the counters for the specified SC, and unpack them into the
266 * fields of counters.
267 * counters - [OUT] The raw table row data will be unpacked here.
271 struct aq_mss_egress_sc_counters *counters,
274 /*! Read the counters for the specified SA, and unpack them into the
275 * fields of counters.
276 * counters - [OUT] The raw table row data will be unpacked here.
280 struct aq_mss_egress_sa_counters *counters,
283 /*! Read the counters for the common egress counters, and unpack them
284 * into the fields of counters.
[all …]
/linux/tools/perf/pmu-events/arch/x86/alderlake/
H A Dcache.json7 "PublicDescription": "L1D.HWPF_MISS Available PDIST counters: 0",
17 …and replacements that require stall-for-replace or block-for-replace. Available PDIST counters: 0",
27 …cheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: 0",
39 …cheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: 0",
50 …"This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS Available PDIST counters: 0",
60 …cheable/uncacheable demand load, store, lock or SW prefetch accesses. Available PDIST counters: 0",
70 …ne splits and reads due to page walks resulted from any request type. Available PDIST counters: 0",
81 …blicDescription": "Counts duration of L1D miss outstanding in cycles. Available PDIST counters: 0",
91 …er of L2 cache lines filling the L2. Counting does not cover rejects. Available PDIST counters: 0",
101 …se lines are in Modified state. Modified lines are written back to L3 Available PDIST counters: 0",
[all …]
H A Dpipeline.json9 …tion": "This event is deprecated. Refer to new event ARITH.DIV_ACTIVE Available PDIST counters: 0",
30 … root operations. Accounts for integer and floating-point operations. Available PDIST counters: 0",
60 …on": "This event is deprecated. Refer to new event ARITH.FPDIV_ACTIVE Available PDIST counters: 0",
81 …cription": "This event counts the cycles the integer divider is busy. Available PDIST counters: 0",
111 …ion": "This event is deprecated. Refer to new event ARITH.IDIV_ACTIVE Available PDIST counters: 0",
121 … Examples include AD (page Access Dirty), FP and AVX related assists. Available PDIST counters: 0",
140 "PublicDescription": "Counts all branch instructions retired. Available PDIST counters: 0",
168 …"PublicDescription": "Counts conditional branch instructions retired. Available PDIST counters: 0",
178 … "PublicDescription": "Counts not taken branch instructions retired. Available PDIST counters: 0",
197 …cDescription": "Counts taken conditional branch instructions retired. Available PDIST counters: 0",
[all …]

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