xref: /linux/tools/perf/pmu-events/arch/x86/graniterapids/virtual-memory.json (revision ab93e0dd72c37d378dd936f031ffb83ff2bd87ce) !

[
    {
        "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
        "Counter": "0,1,2,3",
        "EventCode": "0x12",
        "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
        "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB). Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x12",
        "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
        "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
        "Counter": "0,1,2,3",
        "EventCode": "0x12",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
        "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0xe"
    },
    {
        "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
        "Counter": "0,1,2,3",
        "EventCode": "0x12",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
        "PublicDescription": "Counts completed page walks  (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
        "Counter": "0,1,2,3",
        "EventCode": "0x12",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
        "PublicDescription": "Counts completed page walks  (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
        "Counter": "0,1,2,3",
        "EventCode": "0x12",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
        "PublicDescription": "Counts completed page walks  (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
        "Counter": "0,1,2,3",
        "EventCode": "0x12",
        "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
        "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
        "Counter": "0,1,2,3",
        "EventCode": "0x13",
        "EventName": "DTLB_STORE_MISSES.STLB_HIT",
        "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB). Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x13",
        "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
        "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
        "Counter": "0,1,2,3",
        "EventCode": "0x13",
        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
        "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0xe"
    },
    {
        "BriefDescription": "Page walks completed due to a demand data store to a 1G page.",
        "Counter": "0,1,2,3",
        "EventCode": "0x13",
        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
        "PublicDescription": "Counts completed page walks  (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
        "Counter": "0,1,2,3",
        "EventCode": "0x13",
        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
        "PublicDescription": "Counts completed page walks  (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
        "Counter": "0,1,2,3",
        "EventCode": "0x13",
        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
        "PublicDescription": "Counts completed page walks  (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
        "Counter": "0,1,2,3",
        "EventCode": "0x13",
        "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
        "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
        "Counter": "0,1,2,3",
        "EventCode": "0x11",
        "EventName": "ITLB_MISSES.STLB_HIT",
        "PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB). Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x11",
        "EventName": "ITLB_MISSES.WALK_ACTIVE",
        "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
        "Counter": "0,1,2,3",
        "EventCode": "0x11",
        "EventName": "ITLB_MISSES.WALK_COMPLETED",
        "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0xe"
    },
    {
        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
        "Counter": "0,1,2,3",
        "EventCode": "0x11",
        "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
        "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
        "Counter": "0,1,2,3",
        "EventCode": "0x11",
        "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
        "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.",
        "Counter": "0,1,2,3",
        "EventCode": "0x11",
        "EventName": "ITLB_MISSES.WALK_PENDING",
        "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x10"
    }
]