Home
last modified time | relevance | path

Searched full:ctl2 (Results 1 – 25 of 31) sorted by relevance

12

/linux/tools/testing/selftests/kvm/x86/ !
H A Ducna_injection_test.c79 uint64_t ctl2; in ucna_injection_guest_code() local
85 ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK)); in ucna_injection_guest_code()
86 wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_CMCI_EN); in ucna_injection_guest_code()
97 ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK)); in ucna_injection_guest_code()
98 wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 & ~MCI_CTL2_CMCI_EN); in ucna_injection_guest_code()
109 uint64_t ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK)); in cmci_disabled_guest_code() local
110 wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_CMCI_EN); in cmci_disabled_guest_code()
117 uint64_t ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK)); in cmci_enabled_guest_code() local
118 wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_RESERVED_BIT); in cmci_enabled_guest_code()
/linux/drivers/firmware/cirrus/test/ !
H A Dcs_dsp_test_control_parse.c984 struct cs_dsp_coeff_ctl *walkctl, *ctl1, *ctl2; in cs_dsp_ctl_parse_fw_name() local
1022 ctl2 = NULL; in cs_dsp_ctl_parse_fw_name()
1027 ctl2 = walkctl; in cs_dsp_ctl_parse_fw_name()
1031 KUNIT_EXPECT_NOT_NULL(test, ctl2); in cs_dsp_ctl_parse_fw_name()
1033 KUNIT_EXPECT_EQ(test, ctl2->offset, 2); in cs_dsp_ctl_parse_fw_name()
1042 struct cs_dsp_coeff_ctl *ctl1, *ctl2; in cs_dsp_ctl_alg_id_uniqueness() local
1066 ctl2 = list_next_entry(ctl1, list); in cs_dsp_ctl_alg_id_uniqueness()
1068 KUNIT_EXPECT_NOT_NULL(test, ctl2); in cs_dsp_ctl_alg_id_uniqueness()
1069 KUNIT_EXPECT_NE(test, ctl1->alg_region.alg, ctl2->alg_region.alg); in cs_dsp_ctl_alg_id_uniqueness()
1070 KUNIT_EXPECT_EQ(test, ctl1->alg_region.type, ctl2->alg_region.type); in cs_dsp_ctl_alg_id_uniqueness()
[all …]
/linux/drivers/gpu/drm/i915/display/ !
H A Dintel_backlight.c617 u32 ctl, ctl2, freq; in i965_enable_backlight() local
619 ctl2 = intel_de_read(display, BLC_PWM_CTL2); in i965_enable_backlight()
620 if (ctl2 & BLM_PWM_ENABLE) { in i965_enable_backlight()
624 ctl2 &= ~BLM_PWM_ENABLE; in i965_enable_backlight()
625 intel_de_write(display, BLC_PWM_CTL2, ctl2); in i965_enable_backlight()
635 ctl2 = BLM_PIPE(pipe); in i965_enable_backlight()
637 ctl2 |= BLM_COMBINATION_MODE; in i965_enable_backlight()
639 ctl2 |= BLM_POLARITY_I965; in i965_enable_backlight()
640 intel_de_write(display, BLC_PWM_CTL2, ctl2); in i965_enable_backlight()
642 intel_de_write(display, BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE); in i965_enable_backlight()
[all …]
H A Ddvo_tfp410.c209 u8 ctl2; in tfp410_detect() local
211 if (tfp410_readb(dvo, TFP410_CTL_2, &ctl2)) { in tfp410_detect()
212 if (ctl2 & TFP410_CTL_2_RSEN) in tfp410_detect()
H A Dintel_backlight_regs.h79 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
H A Dintel_ddi.c628 u32 ctl2 = 0; in intel_ddi_enable_transcoder_func() local
634 ctl2 |= PORT_SYNC_MODE_ENABLE | in intel_ddi_enable_transcoder_func()
640 ctl2); in intel_ddi_enable_transcoder_func()
3926 u32 ctl2 = intel_de_read(display, in bdw_transcoder_master_readout() local
3929 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) in bdw_transcoder_master_readout()
3932 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); in bdw_transcoder_master_readout()
/linux/drivers/mtd/nand/raw/ !
H A Dcafe_nand.c66 uint32_t ctl2; member
174 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2); in cafe_nand_cmdfunc()
176 cafe->ctl2 &= ~(1<<30); in cafe_nand_cmdfunc()
243 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2); in cafe_nand_cmdfunc()
245 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2); in cafe_nand_cmdfunc()
248 cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n", in cafe_nand_cmdfunc()
298 WARN_ON(cafe->ctl2 & (1<<30)); in cafe_nand_cmdfunc()
310 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); in cafe_nand_cmdfunc()
314 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); in cafe_nand_cmdfunc()
544 cafe->ctl2 |= (1<<30); in cafe_nand_write_page_lowlevel()
[all …]
/linux/drivers/rtc/ !
H A Drtc-rs5c348.c79 txbuf[0] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */ in rs5c348_rtc_set_time()
81 txbuf[2] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */ in rs5c348_rtc_set_time()
124 txbuf[0] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */ in rs5c348_rtc_read_time()
126 txbuf[2] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */ in rs5c348_rtc_read_time()
/linux/drivers/hwmon/ !
H A Dlm93.c291 * The two PWM CTL2 registers can read something other than what was
1752 u8 ctl2, ctl4; in pwm_show() local
1755 ctl2 = data->block9[nr][LM93_PWM_CTL2]; in pwm_show()
1757 if (ctl2 & 0x01) /* show user commanded value if enabled */ in pwm_show()
1760 rc = LM93_PWM_FROM_REG(ctl2 >> 4, (ctl4 & 0x07) ? in pwm_show()
1771 u8 ctl2, ctl4; in pwm_store() local
1780 ctl2 = lm93_read_byte(client, LM93_REG_PWM_CTL(nr, LM93_PWM_CTL2)); in pwm_store()
1782 ctl2 = (ctl2 & 0x0f) | LM93_PWM_TO_REG(val, (ctl4 & 0x07) ? in pwm_store()
1785 data->pwm_override[nr] = LM93_PWM_FROM_REG(ctl2 >> 4, in pwm_store()
1788 lm93_write_byte(client, LM93_REG_PWM_CTL(nr, LM93_PWM_CTL2), ctl2); in pwm_store()
[all …]
/linux/drivers/video/fbdev/ !
H A Darcfb.c394 unsigned char ctl2; in arcfb_ioctl() local
396 ctl2 = ks108_readb_ctl2(info->par); in arcfb_ioctl()
397 if (copy_to_user(argp, &ctl2, sizeof(ctl2))) in arcfb_ioctl()
/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl/ !
H A Dhw_atl_a0.c455 txd->ctl2 = 0; in hw_atl_a0_hw_ring_tx_xmit()
465 txd->ctl2 |= (buff->mss << 16) | in hw_atl_a0_hw_ring_tx_xmit()
484 txd->ctl2 |= HW_ATL_A0_TXD_CTL2_LEN & (pkt_len << 14); in hw_atl_a0_hw_ring_tx_xmit()
488 txd->ctl2 |= HW_ATL_A0_TXD_CTL2_CTX_EN; in hw_atl_a0_hw_ring_tx_xmit()
H A Dhw_atl_utils.h21 u32 ctl2; /* 63..46 - payload length, 45 - ctx enable, 44 - ctx index */ member
/linux/drivers/pci/pcie/ !
H A Daspm.c641 u32 ctl1 = 0, ctl2 = 0; in aspm_calc_l12_info() local
658 ctl2 |= FIELD_PREP(PCI_L1SS_CTL2_T_PWR_ON_SCALE, scale1) | in aspm_calc_l12_info()
662 ctl2 |= FIELD_PREP(PCI_L1SS_CTL2_T_PWR_ON_SCALE, scale2) | in aspm_calc_l12_info()
690 ctl2 == pctl2 && ctl2 == cctl2) in aspm_calc_l12_info()
707 pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, ctl2); in aspm_calc_l12_info()
708 pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2); in aspm_calc_l12_info()
/linux/drivers/dma/ !
H A Dpch_dma.c183 val = dma_readl(pd, CTL2); in pdc_enable_irq()
190 dma_writel(pd, CTL2, val); in pdc_enable_irq()
741 pd->regs.dma_ctl2 = dma_readl(pd, CTL2); in pch_dma_save_regs()
764 dma_writel(pd, CTL2, pd->regs.dma_ctl2); in pch_dma_restore_regs()
/linux/drivers/net/wireless/mediatek/mt76/ !
H A Dmt76x02_mac.h145 u8 ctl2; member
/linux/drivers/net/wireless/ath/ath9k/ !
H A Dmac.h283 u32 ctl2; member
321 #define ds_ctl2 u.tx.ctl2
H A Deeprom_4k.c124 PR_EEP("Ant. Diversity ctl2", modal_hdr->antdiv_ctl2); in ath9k_dump_4k_modal_eeprom()
/linux/Documentation/devicetree/bindings/arm/tegra/ !
H A Dnvidia,tegra186-pmc.yaml118 hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst,
/linux/drivers/infiniband/hw/bnxt_re/ !
H A Dqplib_res.c957 u16 ctl2; in bnxt_qplib_determine_atomics() local
967 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctl2); in bnxt_qplib_determine_atomics()
968 return !(ctl2 & PCI_EXP_DEVCTL2_ATOMIC_REQ); in bnxt_qplib_determine_atomics()
/linux/sound/soc/codecs/ !
H A Dcs35l33.h25 #define CS35L33_BST_CTL2 0x0C /* Boost Converter CTL2 */
H A Dcs35l35.h28 #define CS35L35_SP_FMT_CTL2 0x0E /* Serial Port Format CTL2 */
/linux/sound/mips/ !
H A Dhal2.h141 /* Bits in CTL2 register */
/linux/drivers/net/ethernet/marvell/octeontx2/af/ !
H A Drvu_cpt.c957 u64 ctl, ctl2; in rvu_mbox_handler_cpt_lf_reset() local
970 ctl2 = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf)); in rvu_mbox_handler_cpt_lf_reset()
978 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), ctl2); in rvu_mbox_handler_cpt_lf_reset()
/linux/drivers/gpu/drm/loongson/ !
H A Dlsdc_regs.h323 * data island. The values of CTL0, CTL1, CTL2, and CTL3 indicate the type of
/linux/drivers/spi/ !
H A Dspi-sprd.c82 /* Bits & mask definition for register CTL2 */

12