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/linux/arch/arm/boot/dts/intel/axm/
H A Daxm5516-cpus.dtsi74 compatible = "arm,cortex-a15";
82 compatible = "arm,cortex-a15";
90 compatible = "arm,cortex-a15";
98 compatible = "arm,cortex-a15";
106 compatible = "arm,cortex-a15";
114 compatible = "arm,cortex-a15";
122 compatible = "arm,cortex-a15";
130 compatible = "arm,cortex-a15";
138 compatible = "arm,cortex-a15";
146 compatible = "arm,cortex-a15";
[all...]
H A Daxm55xx.dtsi56 compatible = "arm,cortex-a15-gic";
83 compatible = "arm,cortex-a15-pmu";
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca15_a7.dts40 compatible = "arm,cortex-a15";
50 compatible = "arm,cortex-a15";
150 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
226 pmu-a15 {
227 compatible = "arm,cortex-a15-pmu";
257 /* A15 PLL 0 reference clock */
266 /* A15 PLL 1 reference clock */
337 regulator-a15 {
338 /* A15 CPU core voltage */
341 regulator-name = "A15 Vcor
[all...]
H A Dvexpress-v2p-ca15-tc1.dts6 * Cortex-A15 MPCore (V2P-CA15)
40 compatible = "arm,cortex-a15";
46 compatible = "arm,cortex-a15";
95 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
136 compatible = "arm,cortex-a15-pmu";
/linux/arch/arm/boot/dts/calxeda/
H A Decx-2000.dts22 compatible = "arm,cortex-a15";
30 compatible = "arm,cortex-a15";
38 compatible = "arm,cortex-a15";
46 compatible = "arm,cortex-a15";
70 compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>,
83 compatible = "arm,cortex-a15-gic";
/linux/arch/arm/boot/dts/amazon/
H A Dalpine.dtsi47 compatible = "arm,cortex-a15";
54 compatible = "arm,cortex-a15";
61 compatible = "arm,cortex-a15";
68 compatible = "arm,cortex-a15";
83 compatible = "arm,cortex-a15-timer",
95 compatible = "arm,cortex-a15-gic";
122 compatible = "arm,cortex-a15-pmu";
/linux/arch/arm/boot/dts/hisilicon/
H A Dhip04.dtsi89 compatible = "arm,cortex-a15";
94 compatible = "arm,cortex-a15";
99 compatible = "arm,cortex-a15";
104 compatible = "arm,cortex-a15";
109 compatible = "arm,cortex-a15";
114 compatible = "arm,cortex-a15";
119 compatible = "arm,cortex-a15";
124 compatible = "arm,cortex-a15";
129 compatible = "arm,cortex-a15";
134 compatible = "arm,cortex-a15";
[all...]
/linux/lib/crypto/arm64/
H A Dchacha-neon-core.S183 a15 .req w28
235 mov a15, v15.s[0]
261 eor a15, a15, a3
270 ror a15, a15, #16
283 add a11, a11, a15
328 eor a15, a15, a3
337 ror a15, a1
[all...]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5420-cpus.dtsi9 * boards: CPU[0123] being the A15.
14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
59 compatible = "arm,cortex-a15";
71 compatible = "arm,cortex-a15";
83 compatible = "arm,cortex-a15";
95 compatible = "arm,cortex-a15";
H A Dexynos5422-cpus.dtsi13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
110 compatible = "arm,cortex-a15";
123 compatible = "arm,cortex-a15";
136 compatible = "arm,cortex-a15";
149 compatible = "arm,cortex-a15";
H A Dexynos5410.dtsi35 compatible = "arm,cortex-a15";
42 compatible = "arm,cortex-a15";
49 compatible = "arm,cortex-a15";
56 compatible = "arm,cortex-a15";
/linux/arch/arm/boot/dts/xen/
H A Dxenvm-4.2.dts6 * Cortex-A15 MPCore (V2P-CA15)
30 compatible = "arm,cortex-a15";
36 compatible = "arm,cortex-a15";
55 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
/linux/arch/arm/mach-sunxi/
H A Dheadsmp.S9 * SMP support for sunxi based systems with Cortex A7/A15
23 * Cortex-A15. These settings are from the vendor kernel.
34 /* The following is Cortex-A15 specific */
55 /* End of Cortex-A15 specific setup */
/linux/arch/xtensa/lib/
H A Dumulsidi3.S19 s32i a15, sp, 28
113 set_arg_ ## yhalf (a15, yreg); \
155 l32i a15, sp, 28
194 result is returned in a12, and a8 and a15 are clobbered. */
223 mul_mulsi3_body a12, a13, a14, a15, a8
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic.yaml30 - arm,cortex-a15-gic
44 - arm,cortex-a15-gic
53 - const: arm,cortex-a15-gic
132 - const: PERIPHCLKEN # for "arm,cortex-a15-gic"
204 compatible = "arm,cortex-a15-gic";
/linux/arch/arm/include/debug/
H A Dexynos.S23 teq \tmp, #0xf0 @@ A15
27 teq \tmp, #0x100 @@ A15 + A7 but boot to A7
/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2hk.dtsi21 compatible = "arm,cortex-a15";
27 compatible = "arm,cortex-a15";
33 compatible = "arm,cortex-a15";
39 compatible = "arm,cortex-a15";
/linux/Documentation/devicetree/bindings/cpu/
H A Dcpu-capacity.txt206 compatible = "arm,cortex-a15";
213 compatible = "arm,cortex-a15";
220 compatible = "arm,cortex-a15";
227 compatible = "arm,cortex-a15";
/linux/Documentation/devicetree/bindings/timer/
H A Darm,arch_timer.yaml25 - const: arm,cortex-a15-timer
119 compatible = "arm,cortex-a15-timer",
/linux/arch/arm/boot/dts/mediatek/
H A Dmt8135.dtsi59 compatible = "arm,cortex-a15";
65 compatible = "arm,cortex-a15";
212 compatible = "arm,cortex-a15-gic";
/linux/Documentation/devicetree/bindings/arm/
H A Darm,vexpress-juno.yaml57 - description: Coretile Express A15x2 (V2P-CA15) has 2 Cortex A15 CPU
64 A15 CPU cores in a test chip on the core tile. This is the first test
70 - description: Coretile Express A15x2 A7x3 (V2P-CA15_A7) has 2 Cortex A15
H A Darm,cci-400.yaml147 compatible = "arm,cortex-a15";
154 compatible = "arm,cortex-a15";
/linux/arch/arm/mach-exynos/
H A Dmcpm-exynos.c71 * This assumes the cluster number of the big cores(Cortex A15) in exynos_cpu_powerup()
143 * On the Cortex-A15 we need to disable in exynos_cluster_cache_disable()
284 * On Exynos5420/5800 for the A15 and A7 clusters: in exynos_mcpm_init()
/linux/arch/xtensa/kernel/
H A Dentry.S186 s32i a15, a1, PT_AREG15
326 s32i a15, a1, PT_AREG15
737 l32i a15, a1, PT_AREG15
1139 * a4..a15: unchanged
1253 /* The spill routine might clobber a4, a7, a8, a11, a12, and a15. */
1260 s32i a15, a2, PT_AREG15
1354 s32e a15, a8, -20
1355 srli a15, a3, 3
1407 l32i a15, a2, PT_AREG15
2054 s32i a15, s
[all...]
/linux/arch/arm/mach-shmobile/
H A Dheadsmp-apmu.S3 * SMP support for APMU based systems with Cortex A7/A15

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