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/linux/arch/arm/mach-davinci/
H A Dda850.c46 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
47 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
48 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
49 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
51 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
52 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
54 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
55 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
57 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
58 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
[all …]
/linux/tools/testing/selftests/hid/tests/
H A Dtest_multitouch.py44 "TOUCH_SIZE_SCALING": BIT(15),
66 self.tippressure = 15
496 …15 00 25 01 95 03 75 01 81 02 95 05 81 03 05 01 15 00 26 ff 0f 55 0e 65 11 75 10 95 01 35 00 46 c8…
917 t1 = Touch(1, 15, 20)
1137 …15 00 25 01 81 02 95 07 75 01 81 03 95 01 75 08 81 03 05 01 09 30 09 31 15 00 26 ff 7f 35 00 46 00…
1148 …15 00 25 01 81 02 95 07 75 01 81 03 95 01 75 08 81 03 05 01 09 30 09 31 15 00 26 ff 7f 35 00 46 00…
1159 …15 00 25 01 75 01 95 01 81 02 09 32 81 02 09 47 81 02 95 05 81 03 09 51 75 08 95 01 81 02 05 01 35…
1196 …rdesc="05 0d 09 04 a1 01 85 01 09 22 a1 02 09 42 15 00 25 01 95 01 75 01 81 02 09 32 81 02 09 47 8…
1206 …15 00 25 01 75 01 95 01 81 02 09 32 81 02 09 47 81 02 95 05 81 03 09 51 75 08 95 01 81 02 05 01 35…
1215 …rdesc="05 0d 09 04 a1 01 85 01 09 22 a1 00 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 09 37 8…
[all …]
H A Dtest_tablet.py457 self.tippressure = 15
1358 …15 00 25 01 75 01 95 01 81 02 09 32 15 00 25 01 81 02 09 51 75 05 95 01 16 00 00 26 10 00 81 02 09…
1366 …15 00 25 01 75 01 95 01 81 02 09 32 15 00 25 01 81 02 09 51 75 05 95 01 16 00 00 26 10 00 81 02 09…
1374 …15 00 25 01 75 01 95 01 81 02 09 32 15 00 25 01 81 02 09 51 75 05 95 01 16 00 00 26 10 00 81 02 09…
1382 …15 00 25 01 75 01 95 01 81 02 09 32 15 00 25 01 81 02 09 51 75 05 95 01 16 00 00 26 10 00 81 02 09…
1390 …15 00 25 01 75 01 95 01 81 02 09 32 15 00 25 01 81 02 09 51 75 05 95 01 16 00 00 26 10 00 81 02 09…
1398 …15 00 25 01 75 01 95 01 81 02 09 32 15 00 25 01 81 02 09 51 75 05 95 01 16 00 00 26 10 00 81 02 09…
1406 …15 00 25 01 95 02 75 01 81 02 95 06 81 03 05 01 09 30 09 31 15 00 26 ff 7f 75 10 95 02 81 02 c0 c0…
1414 …15 00 25 01 75 01 95 01 81 02 09 32 81 02 95 06 81 03 75 08 09 51 95 01 81 02 05 01 26 ff 3f 75 10…
1423 …15 00 25 01 75 01 95 01 81 02 09 32 81 02 95 06 81 03 75 08 09 51 95 01 81 02 05 01 26 ff 3f 75 10…
[all …]
/linux/arch/powerpc/crypto/
H A Daes-gcm-p10.S69 SAVE_GPR 15, 120, 1
111 RESTORE_GPR 15, 120, 1
152 AES_CIPHER_8x vcipher, 15, 23
153 AES_CIPHER_8x vcipher, 15, 24
154 AES_CIPHER_8x vcipher, 15, 25
155 AES_CIPHER_8x vcipher, 15, 26
160 AES_CIPHER_8x vcipher, 15, 23
161 AES_CIPHER_8x vcipher, 15, 24
162 AES_CIPHER_8x vcipher, 15, 25
163 AES_CIPHER_8x vcipher, 15, 26
[all …]
/linux/drivers/gpu/drm/display/
H A Ddrm_dsc_helper.c154 /* PPS 14, 15 */ in drm_dsc_pps_payload_pack()
244 * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0] in drm_dsc_pps_payload_pack()
360 { 683, 15, 6144, 3, 13, 11, 11, {
364 { 10, 13, -12 }, { 12, 14, -12 }, { 15, 15, -12 }
374 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
380 { 512, 12, 6144, 7, 16, 15, 15, {
387 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
396 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
398 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
409 { 5, 12, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
[all …]
/linux/include/linux/mfd/wm831x/
H A Dotp.h19 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
20 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
21 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
26 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
27 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
28 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
33 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
34 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
35 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
40 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
[all …]
H A Dregulator.h18 #define WM831X_CS1_ENA_SHIFT 15 /* CS1_ENA */
43 #define WM831X_CS2_ENA_SHIFT 15 /* CS2_ENA */
256 #define WM831X_INTLDO_UV_STS_SHIFT 15 /* INTLDO_UV_STS */
302 #define WM831X_DC1_RATE_MASK 0xC000 /* DC1_RATE - [15:14] */
303 #define WM831X_DC1_RATE_SHIFT 14 /* DC1_RATE - [15:14] */
304 #define WM831X_DC1_RATE_WIDTH 2 /* DC1_RATE - [15:14] */
326 #define WM831X_DC1_ERR_ACT_MASK 0xC000 /* DC1_ERR_ACT - [15:14] */
327 #define WM831X_DC1_ERR_ACT_SHIFT 14 /* DC1_ERR_ACT - [15:14] */
328 #define WM831X_DC1_ERR_ACT_WIDTH 2 /* DC1_ERR_ACT - [15:14] */
350 #define WM831X_DC1_ON_SLOT_MASK 0xE000 /* DC1_ON_SLOT - [15:13] */
[all …]
/linux/arch/arm64/include/asm/
H A Dapple_m1_pmu.h10 #define SYS_IMP_APL_PMC0_EL1 sys_reg(3, 2, 15, 0, 0)
11 #define SYS_IMP_APL_PMC1_EL1 sys_reg(3, 2, 15, 1, 0)
12 #define SYS_IMP_APL_PMC2_EL1 sys_reg(3, 2, 15, 2, 0)
13 #define SYS_IMP_APL_PMC3_EL1 sys_reg(3, 2, 15, 3, 0)
14 #define SYS_IMP_APL_PMC4_EL1 sys_reg(3, 2, 15, 4, 0)
15 #define SYS_IMP_APL_PMC5_EL1 sys_reg(3, 2, 15, 5, 0)
16 #define SYS_IMP_APL_PMC6_EL1 sys_reg(3, 2, 15, 6, 0)
17 #define SYS_IMP_APL_PMC7_EL1 sys_reg(3, 2, 15, 7, 0)
18 #define SYS_IMP_APL_PMC8_EL1 sys_reg(3, 2, 15, 9, 0)
19 #define SYS_IMP_APL_PMC9_EL1 sys_reg(3, 2, 15, 10, 0)
[all …]
/linux/drivers/infiniband/hw/irdma/
H A Di40iw_hw.h38 #define I40E_GLPES_PFIP4RXDISCARD(_i) (0x00010600 + ((_i) * 4)) /* _i=0...15 */ /* Reset…
39 #define I40E_GLPES_PFIP4RXTRUNC(_i) (0x00010700 + ((_i) * 4)) /* _i=0...15 */ /* Reset…
40 #define I40E_GLPES_PFIP4TXNOROUTE(_i) (0x00012E00 + ((_i) * 4)) /* _i=0...15 */ /* Reset…
41 #define I40E_GLPES_PFIP6RXDISCARD(_i) (0x00011200 + ((_i) * 4)) /* _i=0...15 */ /* Reset…
42 #define I40E_GLPES_PFIP6RXTRUNC(_i) (0x00011300 + ((_i) * 4)) /* _i=0...15 */ /* Reset…
44 #define I40E_GLPES_PFRDMAVBNDLO(_i) (0x00014800 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
45 #define I40E_GLPES_PFIP4TXMCOCTSLO(_i) (0x00012000 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
46 #define I40E_GLPES_PFIP6RXMCOCTSLO(_i) (0x00011600 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
47 #define I40E_GLPES_PFIP6TXMCOCTSLO(_i) (0x00012A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
48 #define I40E_GLPES_PFUDPRXPKTSLO(_i) (0x00013800 + ((_i) * 8)) /* _i=0...15 */ /* Reset…
[all …]
/linux/arch/s390/include/asm/
H A Dfpu-insn-asm.h76 \opd = 15
140 \opd = 15
203 * are stored in instruction bits 12-15.
274 .word (0xE700 | ((v1&15) << 4))
290 .word 0xE700 | ((v1&15) << 4) | r3
311 .word 0xE700 | ((v1&15) << 4) | (v2&15)
321 .word 0xE700 | ((v1&15) << 4) | x2
331 .word 0xE700 | ((v1&15) << 4) | x2
351 .word 0xE700 | ((v1&15) << 4)
373 .word 0xE700 | (r1 << 4) | (v3&15)
[all …]
/linux/tools/accounting/
H A Dgetdelays.c248 printf("%-10s%15s%15s%15s%15s%15s%15s%15s%25s\n", \
252 printf(" %15llu%15llu%15llu%15llu%15.3fms%13.6fms%13.6fms%23s\n", \
262 printf("%-10s%15s%15s%15s%15s%15s%15s%15s\n", \
265 printf(" %15llu%15llu%15llu%15llu%15.3fms%13.6fms%13.6fms\n", \
274 printf("%-10s%15s%15s%15s%15s%15s\n", \
277 printf(" %15llu%15llu%15llu%15llu%15.3fms\n", \
288 printf("%-10s%15s%15s%15s%15s%15s\n", \
291 printf(" %15llu%15llu%15.3fms%13.6fms%13.6fms\n", \
298 printf("%-10s%15s%15s%15s\n", \
300 printf(" %15llu%15llu%15.3fms\n", \
[all …]
/linux/arch/csky/abiv2/inc/abi/
H A Dckmmu.h11 return mfcr("cr<0, 15>"); in read_mmu_index()
16 mtcr("cr<0, 15>", value); in write_mmu_index()
21 return mfcr("cr<2, 15>"); in read_mmu_entrylo0()
26 return mfcr("cr<3, 15>"); in read_mmu_entrylo1()
31 mtcr("cr<6, 15>", value); in write_mmu_pagemask()
36 return mfcr("cr<4, 15>"); in read_mmu_entryhi()
41 mtcr("cr<4, 15>", value); in write_mmu_entryhi()
46 return mfcr("cr<30, 15>"); in read_mmu_msa0()
51 mtcr("cr<30, 15>", value); in write_mmu_msa0()
56 return mfcr("cr<31, 15>"); in read_mmu_msa1()
[all …]
/linux/sound/soc/codecs/
H A Dwm5100.h893 #define WM5100_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */
894 #define WM5100_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */
895 #define WM5100_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */
1102 #define WM5100_ISRC1_INT1_ENA_SHIFT 15 /* ISRC1_INT1_ENA */
1159 #define WM5100_ISRC2_INT1_ENA_SHIFT 15 /* ISRC2_INT1_ENA */
1215 #define WM5100_FLL1_THETA_MASK 0xFFFF /* FLL1_THETA - [15:0] */
1216 #define WM5100_FLL1_THETA_SHIFT 0 /* FLL1_THETA - [15:0] */
1217 #define WM5100_FLL1_THETA_WIDTH 16 /* FLL1_THETA - [15:0] */
1239 #define WM5100_FLL1_LAMBDA_MASK 0xFFFF /* FLL1_LAMBDA - [15:0] */
1240 #define WM5100_FLL1_LAMBDA_SHIFT 0 /* FLL1_LAMBDA - [15:0] */
[all …]
H A Dwm9081.h90 #define WM9081_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */
91 #define WM9081_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */
92 #define WM9081_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */
348 #define WM9081_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */
349 #define WM9081_FLL_K_SHIFT 0 /* FLL_K - [15:0] */
350 #define WM9081_FLL_K_WIDTH 16 /* FLL_K - [15:0] */
479 #define WM9081_IRQ_POL_SHIFT 15 /* IRQ_POL */
517 #define WM9081_DRC_ENA_SHIFT 15 /* DRC_ENA */
538 #define WM9081_DRC_ATK_MASK 0xF000 /* DRC_ATK - [15:12] */
539 #define WM9081_DRC_ATK_SHIFT 12 /* DRC_ATK - [15:12] */
[all …]
H A Drt5660.h133 #define RT5660_L_MUTE (0x1 << 15)
134 #define RT5660_L_MUTE_SFT 15
147 #define RT5660_IN_DF1 (0x1 << 15)
148 #define RT5660_IN_SFT1 15
157 #define RT5660_IN_DF3 (0x1 << 15)
158 #define RT5660_IN_SFT3 15
195 #define RT5660_M_ADCMIX_L (0x1 << 15)
196 #define RT5660_M_ADCMIX_L_SFT 15
363 #define RT5660_PWR_I2S1 (0x1 << 15)
364 #define RT5660_PWR_I2S1_BIT 15
[all …]
H A Drt5616.h152 #define RT5616_L_MUTE (0x1 << 15)
153 #define RT5616_L_MUTE_SFT 15
166 #define RT5616_EN_DFO (0x1 << 15)
208 #define RT5616_M_MONO_ADC_L (0x1 << 15)
209 #define RT5616_M_MONO_ADC_L_SFT 15
232 #define RT5616_M_ADCMIX_L (0x1 << 15)
233 #define RT5616_M_ADCMIX_L_SFT 15
286 #define RT5616_M_STO_L_DAC_L (0x1 << 15)
287 #define RT5616_M_STO_L_DAC_L_SFT 15
304 #define RT5616_RXDP_SRC_MASK (0x1 << 15)
[all …]
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-samsung-dcphy.c150 #define PLL_LOCK_CNT(x) FIELD_PREP(GENMASK(15, 0), x)
152 #define PLL_STB_CNT(x) FIELD_PREP(GENMASK(15, 0), x)
160 #define T_PHY_READY(x) FIELD_PREP(GENMASK(15, 0), x)
174 #define T_CLK_ZERO(x) FIELD_PREP(GENMASK(15, 8), x)
177 #define T_HS_EXIT(x) FIELD_PREP(GENMASK(15, 8), x)
184 #define SKEW_CAL_RUN_TIME(x) FIELD_PREP(GENMASK(15, 12), x)
241 #define T_HS_ZERO(x) FIELD_PREP(GENMASK(15, 8), x)
243 #define T_HS_EXIT(x) FIELD_PREP(GENMASK(15, 8), x)
556 {4260, 21, 75, 20, 18, 20, 35, 17, 15, 29, 24},
557 {4250, 20, 76, 20, 18, 20, 35, 17, 15, 29, 24},
[all …]
/linux/lib/zstd/compress/
H A Dclevels.h29 { 20, 15, 16, 1, 6, 0, ZSTD_fast }, /* level 2 */
42 { 22, 23, 23, 6, 5, 32, ZSTD_btlazy2 }, /* level 15 */
68 { 18, 18, 19, 6, 3,128, ZSTD_btopt }, /* level 15.*/
81 { 17, 13, 15, 1, 5, 0, ZSTD_fast }, /* level 2 */
82 { 17, 15, 16, 2, 5, 0, ZSTD_dfast }, /* level 3 */
94 { 17, 18, 17, 6, 3,256, ZSTD_btopt }, /* level 15.*/
106 { 14, 14, 15, 1, 5, 0, ZSTD_fast }, /* level 1 */
107 { 14, 14, 15, 1, 4, 0, ZSTD_fast }, /* level 2 */
108 { 14, 14, 15, 2, 4, 0, ZSTD_dfast }, /* level 3 */
114 { 14, 15, 14, 5, 4, 8, ZSTD_btlazy2 }, /* level 9.*/
[all …]
/linux/drivers/iio/adc/
H A Dmt6359-auxadc.c38 #define PMIC_AUXADC_RDY_BIT BIT(15)
45 #define MT6358_IMP1_AUTOREPEAT_EN BIT(15)
48 #define MT6359_IMP1_IRQ_RDY BIT(15)
209 MTK_PMIC_IIO_CHAN(MT6357, bat_adc, BATADC, 0, 15, IIO_RESISTANCE),
216 MTK_PMIC_IIO_CHAN(MT6357, tsx_temp, TSX_TEMP, 7, 15, IIO_TEMP),
217 MTK_PMIC_IIO_CHAN(MT6357, hp_ofs_cal, HPOFS_CAL, 9, 15, IIO_RESISTANCE),
218 MTK_PMIC_IIO_CHAN(MT6357, dcxo_temp, DCXO_TEMP, 36, 15, IIO_TEMP),
223 MTK_PMIC_IIO_CHAN(MT6357, batt_v, VBAT, 0, 15, IIO_VOLTAGE),
255 MTK_PMIC_IIO_CHAN(MT6358, bat_adc, BATADC, 0, 15, IIO_RESISTANCE),
261 MTK_PMIC_IIO_CHAN(MT6358, tsx_temp, TSX_TEMP, 7, 15, IIO_TEMP),
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_qp_tables.c27 /* from BPP 4 to 15 in steps of 0.5 */
100 { 15, 15, 14, 14, 13, 13, 13, 13, 12, 12, 11, 11, 11, 11, 10, 10, 10, 9,
147 { 18, 18, 17, 17, 16, 16, 16, 16, 15, 15, 14, 14, 14, 14, 13, 13, 13,
177 { 15, 15, 14, 14, 13, 13, 13, 13, 13, 13, 12, 12, 12, 11, 11, 10, 10, 9,
180 { 16, 15, 15, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 12, 12, 11, 10,
183 { 16, 16, 15, 15, 14, 14, 14, 14, 14, 14, 13, 13, 13, 12, 12, 11, 11,
186 { 16, 16, 16, 15, 15, 15, 14, 14, 14, 14, 13, 13, 13, 13, 12, 12, 12,
189 { 16, 16, 16, 16, 15, 15, 15, 15, 15, 14, 14, 13, 13, 13, 12, 12, 12,
192 { 17, 17, 17, 17, 16, 16, 15, 15, 15, 15, 14, 14, 14, 14, 13, 13, 12,
195 { 19, 19, 18, 18, 17, 17, 17, 17, 16, 16, 15, 15, 15, 15, 14, 14, 14,
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dsc/
H A Dqp_tables.h31 { 7, { 0, 4, 5, 6, 6, 6, 6, 7, 7, 7, 9, 9, 9, 11, 15} },
32 { 7.5, { 0, 2, 4, 6, 6, 6, 6, 7, 7, 7, 8, 9, 9, 11, 15} },
47 { 15, { 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 6, 6, 6, 8} },
62 { 6, { 4, 6, 8, 8, 9, 9, 9, 10, 11, 12, 12, 12, 12, 13, 15} },
63 { 6.5, { 4, 6, 7, 8, 8, 8, 9, 10, 11, 11, 12, 12, 12, 13, 15} },
80 { 15, { 0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 7, 8, 9} },
103 { 4, {11, 12, 13, 14, 15, 15, 15, 16, 17, 18, 18, 19, 19, 21, 22} },
104 { 4.5, {10, 11, 12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 21} },
105 { 5, { 9, 11, 12, 13, 14, 15, 15, 16, 17, 17, 18, 18, 19, 20, 21} },
106 { 5.5, { 8, 10, 11, 12, 13, 14, 15, 16, 16, 17, 17, 18, 18, 19, 20} },
[all …]
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dp_reg.h21 #define DA_XTP_GLB_CKDET_EN_FORCE_VAL BIT(15)
38 #define RG_XTP_LN0_TX_IMPSEL_PMOS GENMASK(15, 12)
41 #define RG_XTP_LN1_TX_IMPSEL_PMOS GENMASK(15, 12)
44 #define RG_XTP_LN2_TX_IMPSEL_PMOS GENMASK(15, 12)
47 #define RG_XTP_LN3_TX_IMPSEL_PMOS GENMASK(15, 12)
91 #define HTOTAL_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
93 #define VTOTAL_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
95 #define HSTART_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
97 #define VSTART_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
99 #define HWIDTH_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
[all …]
/linux/drivers/net/can/dev/
H A Dlength.c30 15, 15, 15, 15, 15, 15, 15, 15, /* 49 - 56 */
31 15, 15, 15, 15, 15, 15, 15, 15 /* 57 - 64 */
/linux/drivers/video/fbdev/nvidia/
H A Dnv_dma.h57 #define SURFACE_PITCH_SRC 15:0
74 #define CLIP_POINT_X 15:0
77 #define CLIP_SIZE_WIDTH 15:0
88 #define LINE_LINES_POINT0_X 15:0
94 #define BLIT_POINT_SRC_X 15:0
97 #define BLIT_POINT_DST_X 15:0
100 #define BLIT_SIZE_WIDTH 15:0
111 #define RECT_SOLID_RECTS_Y 15:0
117 #define RECT_EXPAND_ONE_COLOR_CLIP_POINT0_X 15:0
123 #define RECT_EXPAND_ONE_COLOR_SIZE_WIDTH 15:0
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Dcam.h39 #define ADDR_CAM_W1_OFFSET GENMASK(15, 8)
50 #define ADDR_CAM_W2_MASK_SEL GENMASK(15, 14)
55 #define ADDR_CAM_W4_SMA1 GENMASK(15, 8)
59 #define ADDR_CAM_W5_SMA5 GENMASK(15, 8)
63 #define ADDR_CAM_W6_TMA3 GENMASK(15, 8)
70 #define ADDR_CAM_W8_LSIG_TXOP BIT(15)
87 #define ADDR_CAM_W9_WAPI BIT(15)
97 #define ADDR_CAM_W10_SEC_ENT0 GENMASK(15, 8)
101 #define ADDR_CAM_W11_SEC_ENT4 GENMASK(15, 8)
105 #define ADDR_CAM_W12_BSSID_OFFSET GENMASK(15, 8)
[all …]

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