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/linux/drivers/net/wireless/intel/iwlwifi/cfg/
H A D9000.c19 #define IWL9000_SMEM_OFFSET 0x400000
20 #define IWL9000_SMEM_LEN 0x68000
43 .mac_addr_from_csr = 0x380,
44 .min_umac_error_event_table = 0x800000,
45 .d3_debug_data_base_addr = 0x401000,
61 .mask = 0xffffffff,
65 .mask = 0xffffffff,
H A D8000.c20 #define IWL8000_NVM_VERSION 0x0a1d
23 #define IWL8260_DCCM_OFFSET 0x800000
24 #define IWL8260_DCCM_LEN 0x18000
25 #define IWL8260_DCCM2_OFFSET 0x880000
26 #define IWL8260_DCCM2_LEN 0x8000
27 #define IWL8260_SMEM_OFFSET 0x400000
28 #define IWL8260_SMEM_LEN 0x68000
53 .min_umac_error_event_table = 0x800000,
/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,lpass-cpu.yaml78 const: 0
81 "^dai-link@[0-9a-f]+$":
254 reg = <0 0x62d87000 0 0x68000>,
255 <0 0x62f00000 0
[all...]
/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dmme0_qm_regs.h22 #define mmMME0_QM_GLBL_CFG0 0x68000
24 #define mmMME0_QM_GLBL_CFG1 0x68004
26 #define mmMME0_QM_GLBL_PROT 0x68008
28 #define mmMME0_QM_GLBL_ERR_CFG 0x6800C
30 #define mmMME0_QM_GLBL_SECURE_PROPS_0 0x68010
32 #define mmMME0_QM_GLBL_SECURE_PROPS_1 0x68014
34 #define mmMME0_QM_GLBL_SECURE_PROPS_2 0x68018
36 #define mmMME0_QM_GLBL_SECURE_PROPS_3 0x6801C
38 #define mmMME0_QM_GLBL_SECURE_PROPS_4 0x6802
[all...]
/linux/drivers/gpu/drm/amd/display/dc/hdcp/
H A Dhdcp_msg.c77 [HDCP_MESSAGE_ID_READ_BKSV] = 0x0,
78 [HDCP_MESSAGE_ID_READ_RI_R0] = 0x8,
79 [HDCP_MESSAGE_ID_READ_PJ] = 0xA,
80 [HDCP_MESSAGE_ID_WRITE_AKSV] = 0x10,
81 [HDCP_MESSAGE_ID_WRITE_AINFO] = 0x15,
82 [HDCP_MESSAGE_ID_WRITE_AN] = 0x18,
83 [HDCP_MESSAGE_ID_READ_VH_X] = 0x20,
84 [HDCP_MESSAGE_ID_READ_VH_0] = 0x20,
85 [HDCP_MESSAGE_ID_READ_VH_1] = 0x24,
86 [HDCP_MESSAGE_ID_READ_VH_2] = 0x2
[all...]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_tv_regs.h12 #define TV_CTL _MMIO(0x68000)
20 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
31 # define TV_OVERSAMPLE_4X (0 << 18)
54 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
57 # define TV_FUSE_STATE_ENABLED (0 << 4)
63 # define TV_TEST_MODE_NORMAL (0 << 0)
65 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
67 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
[all...]
/linux/drivers/parisc/
H A Dsuperio.c32 * Function 0 is an IDE controller. It is identical to a PC87415 IDE
54 * 0x5A: FDC, SP1, IDE1, SP2, IDE2, PAR, Reserved, P92
55 * 0x5B: RTC, 8259, 8254, DMA1, DMA2, KBC, P61, APM
100 outb (OCW3_POLL,IC_PIC1+0); in superio_interrupt()
102 results = inb(IC_PIC1+0); in superio_interrupt()
105 * Bit 7: 1 = active Interrupt; 0 = no Interrupt pending in superio_interrupt()
107 * Bits 2-0: highest priority, active requesting interrupt ID (0-7) in superio_interrupt()
109 if ((results & 0x80) == 0) { in superio_interrupt()
[all...]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-s4.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0x0 0x0>;
30 reg = <0x0 0x1>;
37 reg = <0x0 0x2>;
44 reg = <0x0 0x
[all...]
H A Damlogic-c3.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
53 #clock-cells = <0>;
67 reg = <0x0 0x07f50e00 0x
[all...]
/linux/drivers/gpu/drm/amd/display/modules/hdcp/
H A Dhdcp_ddc.c31 #define HDCP_I2C_ADDR 0x3a /* 0x74 >> 1*/
32 #define KSV_READ_SIZE 0xf /* 0x6803b - 0x6802c */
42 MOD_HDCP_MESSAGE_ID_READ_BKSV = 0,
83 [MOD_HDCP_MESSAGE_ID_READ_BKSV] = 0x0,
84 [MOD_HDCP_MESSAGE_ID_READ_RI_R0] = 0x8,
85 [MOD_HDCP_MESSAGE_ID_WRITE_AKSV] = 0x10,
86 [MOD_HDCP_MESSAGE_ID_WRITE_AINFO] = 0x1
[all...]
/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_4_1_0_offset.h29 // base address: 0x68000
30 #define regDAGB0_RDCLI0 0x0000
31 #define regDAGB0_RDCLI0_BASE_IDX 0
32 #define regDAGB0_RDCLI1 0x0001
33 #define regDAGB0_RDCLI1_BASE_IDX 0
34 #define regDAGB0_RDCLI2 0x0002
35 #define regDAGB0_RDCLI2_BASE_IDX 0
36 #define regDAGB0_RDCLI3 0x0003
37 #define regDAGB0_RDCLI3_BASE_IDX 0
[all...]
H A Dmmhub_3_0_2_offset.h29 // base address: 0x68000
30 #define regDAGB0_RDCLI0 0x0000
31 #define regDAGB0_RDCLI0_BASE_IDX 0
32 #define regDAGB0_RDCLI1 0x0001
33 #define regDAGB0_RDCLI1_BASE_IDX 0
34 #define regDAGB0_RDCLI2 0x0002
35 #define regDAGB0_RDCLI2_BASE_IDX 0
36 #define regDAGB0_RDCLI3 0x0003
37 #define regDAGB0_RDCLI3_BASE_IDX 0
[all...]
H A Dmmhub_3_3_0_offset.h29 // base address: 0x68000
30 #define regDAGB0_RDCLI0 0x0000
32 #define regDAGB0_RDCLI1 0x0001
34 #define regDAGB0_RDCLI2 0x0002
36 #define regDAGB0_RDCLI3 0x0003
38 #define regDAGB0_RDCLI4 0x0004
40 #define regDAGB0_RDCLI5 0x0005
42 #define regDAGB0_RDCLI6 0x0006
44 #define regDAGB0_RDCLI7 0x000
[all...]
H A Dmmhub_3_0_0_offset.h29 // base address: 0x68000
30 #define regDAGB0_RDCLI0 0x0000
31 #define regDAGB0_RDCLI0_BASE_IDX 0
32 #define regDAGB0_RDCLI1 0x0001
33 #define regDAGB0_RDCLI1_BASE_IDX 0
34 #define regDAGB0_RDCLI2 0x0002
35 #define regDAGB0_RDCLI2_BASE_IDX 0
36 #define regDAGB0_RDCLI3 0x0003
37 #define regDAGB0_RDCLI3_BASE_IDX 0
[all...]
H A Dmmhub_2_0_0_offset.h27 // base address: 0x68000
28 #define mmDAGB0_RDCLI0 0x0000
29 #define mmDAGB0_RDCLI0_BASE_IDX 0
30 #define mmDAGB0_RDCLI1 0x0001
31 #define mmDAGB0_RDCLI1_BASE_IDX 0
32 #define mmDAGB0_RDCLI2 0x0002
33 #define mmDAGB0_RDCLI2_BASE_IDX 0
34 #define mmDAGB0_RDCLI3 0x0003
35 #define mmDAGB0_RDCLI3_BASE_IDX 0
[all...]
H A Dmmhub_3_0_1_offset.h29 // base address: 0x68000
30 #define regDAGB0_RDCLI0 0x0000
32 #define regDAGB0_RDCLI1 0x0001
34 #define regDAGB0_RDCLI2 0x0002
36 #define regDAGB0_RDCLI3 0x0003
38 #define regDAGB0_RDCLI4 0x0004
40 #define regDAGB0_RDCLI5 0x0005
42 #define regDAGB0_RDCLI6 0x0006
44 #define regDAGB0_RDCLI7 0x000
[all...]
H A Dmmhub_1_0_offset.h27 // base address: 0x68000
28 #define mmDAGB0_RDCLI0 0x0000
29 #define mmDAGB0_RDCLI0_BASE_IDX 0
30 #define mmDAGB0_RDCLI1 0x0001
31 #define mmDAGB0_RDCLI1_BASE_IDX 0
32 #define mmDAGB0_RDCLI2 0x0002
33 #define mmDAGB0_RDCLI2_BASE_IDX 0
34 #define mmDAGB0_RDCLI3 0x0003
35 #define mmDAGB0_RDCLI3_BASE_IDX 0
[all...]
H A Dmmhub_9_1_offset.h27 // base address: 0x68000
28 #define mmDAGB0_RDCLI0 0x0000
29 #define mmDAGB0_RDCLI0_BASE_IDX 0
30 #define mmDAGB0_RDCLI1 0x0001
31 #define mmDAGB0_RDCLI1_BASE_IDX 0
32 #define mmDAGB0_RDCLI2 0x0002
33 #define mmDAGB0_RDCLI2_BASE_IDX 0
34 #define mmDAGB0_RDCLI3 0x0003
35 #define mmDAGB0_RDCLI3_BASE_IDX 0
[all...]
H A Dmmhub_9_3_0_offset.h27 // base address: 0x68000
28 #define mmDAGB0_RDCLI0 0x0000
29 #define mmDAGB0_RDCLI0_BASE_IDX 0
30 #define mmDAGB0_RDCLI1 0x0001
31 #define mmDAGB0_RDCLI1_BASE_IDX 0
32 #define mmDAGB0_RDCLI2 0x0002
33 #define mmDAGB0_RDCLI2_BASE_IDX 0
34 #define mmDAGB0_RDCLI3 0x0003
35 #define mmDAGB0_RDCLI3_BASE_IDX 0
[all...]
H A Dmmhub_2_3_0_offset.h27 // base address: 0x68000
28 #define mmDAGB0_RDCLI0 0x0000
30 #define mmDAGB0_RDCLI1 0x0001
32 #define mmDAGB0_RDCLI2 0x0002
34 #define mmDAGB0_RDCLI3 0x0003
36 #define mmDAGB0_RDCLI4 0x0004
38 #define mmDAGB0_RDCLI5 0x0005
40 #define mmDAGB0_RDCLI6 0x0006
42 #define mmDAGB0_RDCLI7 0x000
[all...]
/linux/drivers/phy/microchip/
H A Dsparx5_serdes.c31 #define SPX5_SERDES_QUIET_MODE_VAL 0x01ef4e0c
363 .cfg_en_adv = 0,
365 .cfg_en_dly = 0,
366 .cfg_tap_adv_3_0 = 0,
368 .cfg_tap_dly_4_0 = 0,
369 .cfg_eq_c_force_3_0 = 0xf,
378 .cfg_tap_adv_3_0 = 0,
380 .cfg_tap_dly_4_0 = 0x10,
381 .cfg_eq_c_force_3_0 = 0xf,
384 .cfg_alos_thr_2_0 = 0,
[all...]
/linux/drivers/soc/tegra/cbb/
H A Dtegra234-cbb.c8 * Error types supported by CBB2.0 are:
27 #define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0
28 #define FABRIC_EN_CFG_STATUS_0_0 0x40
29 #define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60
30 #define FABRIC_EN_CFG_ADDR_LOW_0 0x80
31 #define FABRIC_EN_CFG_ADDR_HI_0 0x84
33 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_INDEX_0_0 0x100
34 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_LOW_0 0x140
35 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_HI_0 0x144
37 #define FABRIC_MN_INITIATOR_ERR_EN_0 0x20
[all...]
/linux/drivers/net/wireless/ath/ath10k/
H A Dcoredump.c21 {0x800, 0x810},
22 {0x820, 0x82C},
23 {0x830, 0x8F4},
24 {0x90C, 0x91C},
25 {0xA14, 0xA1
[all...]
/linux/include/drm/display/
H A Ddrm_dp.h44 #define DP_MSA_MISC_SYNC_CLOCK (1 << 0)
46 #define DP_MSA_MISC_STEREO_NO_3D (0 << 9)
50 #define DP_MSA_MISC_6_BPC (0 << 5)
66 #define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)
67 #define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)
[all...]
/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A D8192f.c18 {0x420, 0x00}, {0x422, 0x78}, {0x428, 0x0a}, {0x429, 0x10},
19 {0x430, 0x0
[all...]

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