Lines Matching +full:0 +full:x68000
8 * Error types supported by CBB2.0 are:
27 #define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0
28 #define FABRIC_EN_CFG_STATUS_0_0 0x40
29 #define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60
30 #define FABRIC_EN_CFG_ADDR_LOW_0 0x80
31 #define FABRIC_EN_CFG_ADDR_HI_0 0x84
33 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_INDEX_0_0 0x100
34 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_LOW_0 0x140
35 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_HI_0 0x144
37 #define FABRIC_MN_INITIATOR_ERR_EN_0 0x200
38 #define FABRIC_MN_INITIATOR_ERR_FORCE_0 0x204
39 #define FABRIC_MN_INITIATOR_ERR_STATUS_0 0x208
40 #define FABRIC_MN_INITIATOR_ERR_OVERFLOW_STATUS_0 0x20c
42 #define FABRIC_MN_INITIATOR_LOG_ERR_STATUS_0 0x300
43 #define FABRIC_MN_INITIATOR_LOG_ADDR_LOW_0 0x304
44 #define FABRIC_MN_INITIATOR_LOG_ADDR_HIGH_0 0x308
45 #define FABRIC_MN_INITIATOR_LOG_ATTRIBUTES0_0 0x30c
46 #define FABRIC_MN_INITIATOR_LOG_ATTRIBUTES1_0 0x310
47 #define FABRIC_MN_INITIATOR_LOG_ATTRIBUTES2_0 0x314
48 #define FABRIC_MN_INITIATOR_LOG_USER_BITS0_0 0x318
50 #define AXI_SLV_TIMEOUT_STATUS_0_0 0x8
51 #define APB_BLOCK_TMO_STATUS_0 0xc00
52 #define APB_BLOCK_NUM_TMO_OFFSET 0x20
57 #define FAB_EM_EL_FALCONSEC GENMASK(1, 0)
60 #define FAB_EM_EL_TARGETID GENMASK(7, 0)
62 #define FAB_EM_EL_ACCESSID GENMASK(7, 0)
69 #define FAB_EM_EL_ACCESSTYPE GENMASK(0, 0)
75 #define CCPLEX_MSTRID 0x1
76 #define FIREWALL_APERTURE_SZ 0x10000
78 #define WEN 0x20000
237 writel(0, priv->mon + FABRIC_MN_INITIATOR_ERR_FORCE_0);
258 writel(0x1, cbb->regs + cbb->fabric->off_mask_erd);
279 unsigned int block = 0;
289 if (status & BIT(0)) {
290 u32 timeout, clients, client = 0;
297 if (timeout & BIT(0)) {
298 if (clients != 0xffffffff)
384 unsigned int type = 0;
396 if (status & 0x1)
404 type = 0;
413 if (overflow & 0x1)
446 if ((mstr_id != 0x1) && (mstr_id != 0x2) && (mstr_id != 0xB))
498 * For 'ID = 0x4', we must check for the address which caused the error
543 if (status == 0xffffffff) {
558 cbb->type = 0;
561 if (error & BIT(0)) {
581 return 0;
586 unsigned int index = 0;
594 if (status & BIT(0)) {
621 return 0;
629 int err = 0;
668 tegra_cbb_print_err(NULL, "CPU:%d, Error: %s@0x%llx, irq=%d\n",
678 * If illegal request is from CCPLEX(id:0x1) initiator then call WARN()
702 int err = devm_request_irq(cbb->dev, priv->sec_irq, tegra234_cbb_isr, 0,
711 return 0;
731 [0x00] = "TZ",
732 [0x01] = "CCPLEX",
733 [0x02] = "CCPMU",
734 [0x03] = "BPMP_FW",
735 [0x04] = "AON",
736 [0x05] = "SCE",
737 [0x06] = "GPCDMA_P",
738 [0x07] = "TSECA_NONSECURE",
739 [0x08] = "TSECA_LIGHTSECURE",
740 [0x09] = "TSECA_HEAVYSECURE",
741 [0x0a] = "CORESIGHT",
742 [0x0b] = "APE",
743 [0x0c] = "PEATRANS",
744 [0x0d] = "JTAGM_DFT",
745 [0x0e] = "RCE",
746 [0x0f] = "DCE",
747 [0x10] = "PSC_FW_USER",
748 [0x11] = "PSC_FW_SUPERVISOR",
749 [0x12] = "PSC_FW_MACHINE",
750 [0x13] = "PSC_BOOT",
751 [0x14] = "BPMP_BOOT",
752 [0x15] = "NVDEC_NONSECURE",
753 [0x16] = "NVDEC_LIGHTSECURE",
754 [0x17] = "NVDEC_HEAVYSECURE",
755 [0x18] = "CBB_INTERNAL",
756 [0x19] = "RSVD"
782 { "AXI2APB", 0x00000 },
783 { "AST", 0x14000 },
784 { "CBB", 0x15000 },
785 { "CPU", 0x16000 },
789 { "AXI2APB", 0x00000 },
790 { "AST0", 0x15000 },
791 { "AST1", 0x16000 },
792 { "CBB", 0x17000 },
793 { "CPU", 0x18000 },
797 { "AXI2APB", 0x00000 },
798 { "AST0", 0x15000 },
799 { "AST1", 0x16000 },
800 { "CBB", 0x17000 },
801 { "RSVD", 0x00000 },
802 { "CPU", 0x18000 },
806 { "AON", 0x40000 },
807 { "BPMP", 0x41000 },
808 { "CBB", 0x42000 },
809 { "HOST1X", 0x43000 },
810 { "STM", 0x44000 },
811 { "FSI", 0x45000 },
812 { "PSC", 0x46000 },
813 { "PCIE_C1", 0x47000 },
814 { "PCIE_C2", 0x48000 },
815 { "PCIE_C3", 0x49000 },
816 { "PCIE_C0", 0x4a000 },
817 { "PCIE_C4", 0x4b000 },
818 { "GPU", 0x4c000 },
819 { "SMMU0", 0x4d000 },
820 { "SMMU1", 0x4e000 },
821 { "SMMU2", 0x4f000 },
822 { "SMMU3", 0x50000 },
823 { "SMMU4", 0x51000 },
824 { "PCIE_C10", 0x52000 },
825 { "PCIE_C7", 0x53000 },
826 { "PCIE_C8", 0x54000 },
827 { "PCIE_C9", 0x55000 },
828 { "PCIE_C5", 0x56000 },
829 { "PCIE_C6", 0x57000 },
830 { "DCE", 0x58000 },
831 { "RCE", 0x59000 },
832 { "SCE", 0x5a000 },
833 { "AXI2APB_1", 0x70000 },
834 { "AXI2APB_10", 0x71000 },
835 { "AXI2APB_11", 0x72000 },
836 { "AXI2APB_12", 0x73000 },
837 { "AXI2APB_13", 0x74000 },
838 { "AXI2APB_14", 0x75000 },
839 { "AXI2APB_15", 0x76000 },
840 { "AXI2APB_16", 0x77000 },
841 { "AXI2APB_17", 0x78000 },
842 { "AXI2APB_18", 0x79000 },
843 { "AXI2APB_19", 0x7a000 },
844 { "AXI2APB_2", 0x7b000 },
845 { "AXI2APB_20", 0x7c000 },
846 { "AXI2APB_21", 0x7d000 },
847 { "AXI2APB_22", 0x7e000 },
848 { "AXI2APB_23", 0x7f000 },
849 { "AXI2APB_25", 0x80000 },
850 { "AXI2APB_26", 0x81000 },
851 { "AXI2APB_27", 0x82000 },
852 { "AXI2APB_28", 0x83000 },
853 { "AXI2APB_29", 0x84000 },
854 { "AXI2APB_30", 0x85000 },
855 { "AXI2APB_31", 0x86000 },
856 { "AXI2APB_32", 0x87000 },
857 { "AXI2APB_33", 0x88000 },
858 { "AXI2APB_34", 0x89000 },
859 { "AXI2APB_35", 0x92000 },
860 { "AXI2APB_4", 0x8b000 },
861 { "AXI2APB_5", 0x8c000 },
862 { "AXI2APB_6", 0x8d000 },
863 { "AXI2APB_7", 0x8e000 },
864 { "AXI2APB_8", 0x8f000 },
865 { "AXI2APB_9", 0x90000 },
866 { "AXI2APB_3", 0x91000 },
898 .err_intr_enbl = 0x7,
899 .err_status_clr = 0x3f,
900 .notifier_offset = 0x17000,
901 .firewall_base = 0x30000,
902 .firewall_ctl = 0x8d0,
903 .firewall_wr_ctl = 0x8c8,
912 .err_intr_enbl = 0xf,
913 .err_status_clr = 0x3f,
914 .notifier_offset = 0x19000,
915 .firewall_base = 0x30000,
916 .firewall_ctl = 0x8f0,
917 .firewall_wr_ctl = 0x8e8,
926 .err_intr_enbl = 0x7f,
927 .err_status_clr = 0x3f,
928 .notifier_offset = 0x60000,
929 .off_mask_erd = 0x3a004,
930 .firewall_base = 0x10000,
931 .firewall_ctl = 0x23f0,
932 .firewall_wr_ctl = 0x23e8,
941 .err_intr_enbl = 0xf,
942 .err_status_clr = 0x3f,
943 .notifier_offset = 0x19000,
944 .firewall_base = 0x30000,
945 .firewall_ctl = 0x290,
946 .firewall_wr_ctl = 0x288,
955 .err_intr_enbl = 0xf,
956 .err_status_clr = 0x3f,
957 .notifier_offset = 0x19000,
958 .firewall_base = 0x30000,
959 .firewall_ctl = 0x290,
960 .firewall_wr_ctl = 0x288,
969 .err_intr_enbl = 0xf,
970 .err_status_clr = 0x3f,
971 .notifier_offset = 0x19000,
972 .firewall_base = 0x30000,
973 .firewall_ctl = 0x290,
974 .firewall_wr_ctl = 0x288,
978 [0x0] = "TZ",
979 [0x1] = "CCPLEX",
980 [0x2] = "CCPMU",
981 [0x3] = "BPMP_FW",
982 [0x4] = "PSC_FW_USER",
983 [0x5] = "PSC_FW_SUPERVISOR",
984 [0x6] = "PSC_FW_MACHINE",
985 [0x7] = "PSC_BOOT",
986 [0x8] = "BPMP_BOOT",
987 [0x9] = "JTAGM_DFT",
988 [0xa] = "CORESIGHT",
989 [0xb] = "GPU",
990 [0xc] = "PEATRANS",
991 [0xd ... 0x3f] = "RSVD"
1087 { "RSVD", 0x00000 },
1088 { "RSVD", 0x00000 },
1089 { "RSVD", 0x00000 },
1090 { "CBB", 0x15000 },
1091 { "CPU", 0x16000 },
1092 { "AXI2APB", 0x00000 },
1093 { "DBB0", 0x17000 },
1094 { "DBB1", 0x18000 },
1098 { "RSVD", 0x00000 },
1099 { "PCIE_C8", 0x51000 },
1100 { "PCIE_C9", 0x52000 },
1101 { "RSVD", 0x00000 },
1102 { "RSVD", 0x00000 },
1103 { "RSVD", 0x00000 },
1104 { "RSVD", 0x00000 },
1105 { "RSVD", 0x00000 },
1106 { "RSVD", 0x00000 },
1107 { "RSVD", 0x00000 },
1108 { "RSVD", 0x00000 },
1109 { "AON", 0x5b000 },
1110 { "BPMP", 0x5c000 },
1111 { "RSVD", 0x00000 },
1112 { "RSVD", 0x00000 },
1113 { "PSC", 0x5d000 },
1114 { "STM", 0x5e000 },
1115 { "AXI2APB_1", 0x70000 },
1116 { "AXI2APB_10", 0x71000 },
1117 { "AXI2APB_11", 0x72000 },
1118 { "AXI2APB_12", 0x73000 },
1119 { "AXI2APB_13", 0x74000 },
1120 { "AXI2APB_14", 0x75000 },
1121 { "AXI2APB_15", 0x76000 },
1122 { "AXI2APB_16", 0x77000 },
1123 { "AXI2APB_17", 0x78000 },
1124 { "AXI2APB_18", 0x79000 },
1125 { "AXI2APB_19", 0x7a000 },
1126 { "AXI2APB_2", 0x7b000 },
1127 { "AXI2APB_20", 0x7c000 },
1128 { "AXI2APB_4", 0x87000 },
1129 { "AXI2APB_5", 0x88000 },
1130 { "AXI2APB_6", 0x89000 },
1131 { "AXI2APB_7", 0x8a000 },
1132 { "AXI2APB_8", 0x8b000 },
1133 { "AXI2APB_9", 0x8c000 },
1134 { "AXI2APB_3", 0x8d000 },
1135 { "AXI2APB_21", 0x7d000 },
1136 { "AXI2APB_22", 0x7e000 },
1137 { "AXI2APB_23", 0x7f000 },
1138 { "AXI2APB_24", 0x80000 },
1139 { "AXI2APB_25", 0x81000 },
1140 { "AXI2APB_26", 0x82000 },
1141 { "AXI2APB_27", 0x83000 },
1142 { "AXI2APB_28", 0x84000 },
1143 { "PCIE_C4", 0x53000 },
1144 { "PCIE_C5", 0x54000 },
1145 { "PCIE_C6", 0x55000 },
1146 { "PCIE_C7", 0x56000 },
1147 { "PCIE_C2", 0x57000 },
1148 { "PCIE_C3", 0x58000 },
1149 { "PCIE_C0", 0x59000 },
1150 { "PCIE_C1", 0x5a000 },
1151 { "CCPLEX", 0x50000 },
1152 { "AXI2APB_29", 0x85000 },
1153 { "AXI2APB_30", 0x86000 },
1154 { "CBB_CENTRAL", 0x00000 },
1155 { "AXI2APB_31", 0x8E000 },
1156 { "AXI2APB_32", 0x8F000 },
1171 .err_intr_enbl = 0x7,
1172 .err_status_clr = 0x1ff007f,
1173 .notifier_offset = 0x60000,
1174 .off_mask_erd = 0x40004,
1175 .firewall_base = 0x20000,
1176 .firewall_ctl = 0x2370,
1177 .firewall_wr_ctl = 0x2368,
1186 .err_intr_enbl = 0xf,
1187 .err_status_clr = 0x1ff007f,
1188 .notifier_offset = 0x19000,
1189 .firewall_base = 0x30000,
1190 .firewall_ctl = 0x8f0,
1191 .firewall_wr_ctl = 0x8e8,
1195 [0x0] = "TZ",
1196 [0x1] = "CCPLEX",
1197 [0x2] = "ISC",
1198 [0x3] = "BPMP_FW",
1199 [0x4] = "AON",
1200 [0x5] = "MSS_SEQ",
1201 [0x6] = "GPCDMA_P",
1202 [0x7] = "TSECA_NONSECURE",
1203 [0x8] = "TSECA_LIGHTSECURE",
1204 [0x9] = "TSECA_HEAVYSECURE",
1205 [0xa] = "CORESIGHT",
1206 [0xb] = "APE_0",
1207 [0xc] = "APE_1",
1208 [0xd] = "PEATRANS",
1209 [0xe] = "JTAGM_DFT",
1210 [0xf] = "RCE",
1211 [0x10] = "DCE",
1212 [0x11] = "PSC_FW_USER",
1213 [0x12] = "PSC_FW_SUPERVISOR",
1214 [0x13] = "PSC_FW_MACHINE",
1215 [0x14] = "PSC_BOOT",
1216 [0x15] = "BPMP_BOOT",
1217 [0x16] = "GPU_0",
1218 [0x17] = "GPU_1",
1219 [0x18] = "GPU_2",
1220 [0x19] = "GPU_3",
1221 [0x1a] = "GPU_4",
1222 [0x1b] = "PSC_EXT_BOOT",
1223 [0x1c] = "PSC_EXT_RUNTIME",
1224 [0x1d] = "OESP_EXT",
1225 [0x1e] = "SB_EXT",
1226 [0x1f] = "FSI_SAFETY_0",
1227 [0x20] = "FSI_SAFETY_1",
1228 [0x21] = "FSI_SAFETY_2",
1229 [0x22] = "FSI_SAFETY_3",
1230 [0x23] = "FSI_CHSM",
1231 [0x24] = "RCE_1",
1232 [0x25] = "BPMP_OEM_FW",
1233 [0x26 ... 0x3d] = "RSVD",
1234 [0x3e] = "CBB_SMN",
1235 [0x3f] = "CBB_RSVD"
1239 { "RSVD", 0x000000 },
1240 { "CBB_CENTRAL", 0xC020000 },
1241 { "AXI2APB_1", 0x80000 },
1242 { "AXI2APB_10", 0x81000 },
1243 { "AXI2APB_11", 0x82000 },
1244 { "RSVD", 0x00000 },
1245 { "RSVD", 0x00000 },
1246 { "AXI2APB_14", 0x83000 },
1247 { "AXI2APB_15", 0x84000 },
1248 { "AXI2APB_16", 0x85000 },
1249 { "AXI2APB_17", 0x86000 },
1250 { "AXI2APB_2", 0x87000 },
1251 { "AXI2APB_3", 0x88000 },
1252 { "RSVD", 0x00000 },
1253 { "AXI2APB_5", 0x8A000 },
1254 { "AXI2APB_6", 0x8B000 },
1255 { "AXI2APB_7", 0x8C000 },
1256 { "AXI2APB_8", 0x8D000 },
1257 { "AXI2APB_9", 0x8E000 },
1258 { "FSI_SLAVE", 0x64000 },
1259 { "DISP_USB_CBB_T", 0x65000 },
1260 { "SYSTEM_CBB_T", 0x66000 },
1261 { "UPHY0_CBB_T", 0x67000 },
1262 { "VISION_CBB_T", 0x68000 },
1263 { "CCPLEX_SLAVE", 0x69000 },
1264 { "PCIE_C0", 0x6A000 },
1265 { "SMN_UCF_RX_0", 0x6B000 },
1266 { "SMN_UCF_RX_1", 0x6C000 },
1267 { "AXI2APB_4", 0x89000 },
1271 { "RSVD", 0x00000 },
1272 { "AXI2APB_1", 0xE1000 },
1273 { "RSVD", 0x00000 },
1274 { "AON_SLAVE", 0x79000 },
1275 { "APE_SLAVE", 0x73000 },
1276 { "BPMP_SLAVE", 0x74000 },
1277 { "OESP_SLAVE", 0x75000 },
1278 { "PSC_SLAVE", 0x76000 },
1279 { "SB_SLAVE", 0x7A000 },
1280 { "SMN_SYSTEM_RX", 0x7B000 },
1281 { "STM", 0x77000 },
1282 { "RSVD", 0x00000 },
1283 { "AXI2APB_3", 0xE3000 },
1284 { "TOP_CBB_T", 0x7C000 },
1285 { "AXI2APB_2", 0xE4000 },
1286 { "AXI2APB_4", 0xE5000 },
1287 { "AXI2APB_5", 0xE6000 },
1291 [0 ... 20] = { "RSVD", 0x00000 },
1292 { "AXI2APB_1", 0x71000 },
1293 { "RSVD", 0x00000 },
1294 { "AXI2APB_3", 0x75000 },
1295 { "SMN_UPHY0_RX", 0x53000 },
1296 { "RSVD", 0x00000 },
1297 { "RSVD", 0x00000 },
1298 { "RSVD", 0x00000 },
1299 { "RSVD", 0x00000 },
1300 { "PCIE_C4", 0x4B000 },
1301 { "AXI2APB_2", 0x74000 },
1302 { "AXI2APB_4", 0x76000 },
1303 { "AXI2APB_5", 0x77000 },
1304 { "RSVD", 0x00000 },
1305 { "AXI2APB_7", 0x79000 },
1306 { "PCIE_C2", 0x56000 },
1307 { "RSVD", 0x00000 },
1308 { "RSVD", 0x00000 },
1309 { "PCIE_C1", 0x55000 },
1310 { "RSVD", 0x00000 },
1311 { "AXI2APB_10", 0x72000 },
1312 { "AXI2APB_11", 0x7C000 },
1313 { "AXI2APB_8", 0x7A000 },
1314 { "AXI2APB_9", 0x7B000 },
1315 { "RSVD", 0x00000 },
1316 { "RSVD", 0x00000 },
1317 { "PCIE_C5", 0x4E000 },
1318 { "PCIE_C3", 0x58000 },
1319 { "RSVD", 0x00000 },
1320 { "ISC_SLAVE", 0x54000 },
1321 { "TOP_CBB_T", 0x57000 },
1322 { "AXI2APB_12", 0x7D000 },
1323 { "AXI2APB_13", 0x70000 },
1324 { "AXI2APB_6", 0x7E000 },
1328 [0 ... 5] = { "RSVD", 0x0 },
1329 { "HOST1X", 0x45000 },
1330 { "RSVD", 0x00000 },
1331 { "RSVD", 0x00000 },
1332 { "AXI2APB_2", 0x71000 },
1333 { "RSVD", 0x00000 },
1334 { "RSVD", 0x00000 },
1335 { "SMN_VISION_RX", 0x47000 },
1336 [13 ... 19] = { "RSVD", 0x0 },
1337 { "RCE_0_SLAVE", 0x4B000 },
1338 { "RCE_1_SLAVE", 0x4C000 },
1339 { "AXI2APB_1", 0x72000 },
1340 { "AXI2APB_3", 0x73000 },
1341 { "TOP_CBB_T", 0x4D000 },
1379 .err_intr_enbl = 0x7,
1380 .err_status_clr = 0x1ff007f,
1381 .notifier_offset = 0x90000,
1382 .off_mask_erd = 0x4a004,
1383 .firewall_base = 0x3c0000,
1384 .firewall_ctl = 0x5b0,
1385 .firewall_wr_ctl = 0x5a8,
1394 .err_intr_enbl = 0xf,
1395 .err_status_clr = 0x1ff007f,
1396 .notifier_offset = 0x40000,
1397 .firewall_base = 0x29c000,
1398 .firewall_ctl = 0x170,
1399 .firewall_wr_ctl = 0x168,
1408 .err_intr_enbl = 0x1,
1409 .err_status_clr = 0x1ff007f,
1410 .notifier_offset = 0x80000,
1411 .firewall_base = 0x360000,
1412 .firewall_ctl = 0x590,
1413 .firewall_wr_ctl = 0x588,
1422 .err_intr_enbl = 0x1,
1423 .err_status_clr = 0x1ff007f,
1424 .notifier_offset = 0x80000,
1425 .firewall_base = 0x290000,
1426 .firewall_ctl = 0x5d0,
1427 .firewall_wr_ctl = 0x5c8,
1441 .err_intr_enbl = 0xf,
1442 .err_status_clr = 0x1ff007f,
1443 .notifier_offset = 0x50000,
1444 .off_mask_erd = 0x14004,
1445 .firewall_base = 0x40000,
1446 .firewall_ctl = 0x9b0,
1447 .firewall_wr_ctl = 0x9a8,
1455 .err_intr_enbl = 0x1,
1456 .err_status_clr = 0x1ff007f,
1457 .notifier_offset = 0x50000,
1458 .firewall_base = 0x30000,
1459 .firewall_ctl = 0x810,
1460 .firewall_wr_ctl = 0x808,
1468 .err_intr_enbl = 0x1f,
1469 .err_status_clr = 0x1ff007f,
1470 .notifier_offset = 0x50000,
1471 .firewall_base = 0x30000,
1472 .firewall_ctl = 0x930,
1473 .firewall_wr_ctl = 0x928,
1529 unsigned long flags = 0;
1555 cbb->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &cbb->res);
1571 return 0;
1593 return 0;