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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65.dtsi54 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
55 <0x00 0x00600000 0x00 0x0060000
[all...]
H A Dk3-j7200.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xc000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xc000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
113 ranges = <0x0
[all...]
H A Dk3-j784s4-j742s2-common.dtsi27 cache-size = <0x200000>;
37 cache-size = <0x200000>;
80 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
81 <0x00 0x0060000
[all...]
H A Dk3-j721e-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x0 0x1000>;
44 ranges = <0x0 0x0 0x40f00000 0x20000>;
48 reg = <0x200 0x
[all...]
H A Dk3-j7200-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x00 0x1000>;
43 reg = <0x00 0x40400000 0x00 0x400>;
57 reg = <0x00 0x4041000
[all...]
H A Dk3-j784s4-j742s2-mcu-wakeup-common.dtsi19 reg = <0x00 0x44083000 0x00 0x1000>;
44 ranges = <0x0 0x00 0x43000000 0x20000>;
49 reg = <0x14 0x
[all...]
H A Dk3-j721s2-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x00 0x1000>;
44 ranges = <0x0 0x00 0x43000000 0x20000>;
48 reg = <0x14 0x
[all...]
/linux/arch/arm/mach-omap2/
H A Dsram.h57 #define OMAP2_SRAM_PA 0x40200000
58 #define OMAP3_SRAM_PA 0x40200000
/linux/arch/arm64/boot/dts/arm/
H A Dcorstone1000-mps3.dts18 reg = <0x40100000 0x10000>;
27 reg = <0x40200000 0x100000>;
/linux/arch/powerpc/platforms/cell/spufs/
H A Dspu_restore_dump.h_shipped7 0x40800000,
8 0x409ff801,
9 0x24000080,
10 0x24fd8081,
11 0x1cd80081,
12 0x33001180,
13 0x42034003,
14 0x33800284,
15 0x1c010204,
16 0x4020000
[all...]
H A Dspu_save_crt0.S18 .space SIZEOF_SPU_SPILL_REGS, 0x0
24 stqa $0, regs_spill + 0
47 .balignl 16, 0x40200000
49 stqd $16, 0($3)
53 andi $5, $4, 0x7F
62 il $0, 0
64 stqd $0,
[all...]
H A Dspu_restore_crt0.S19 .space SIZEOF_SPU_SPILL_REGS, 0x0
28 il $0, 0
30 stqd $0, 0($SP)
40 brsl $0, main
52 .balignl 16, 0x40200000
54 lqd $16, 0($3)
58 andi $5, $4, 0x7
[all...]
H A Dspu_restore.c15 #define LS_SIZE 0x40000 /* 256K (in bytes) */
25 #define BR_INSTR 0x327fff80 /* br -4 */
26 #define NOP_INSTR 0x40200000 /* nop */
27 #define HEQ_INSTR 0x7b000000 /* heq $0, $0 */
28 #define STOP_INSTR 0x00000000 /* stop 0x0 */
29 #define ILLEGAL_INSTR 0x0080000
[all...]
H A Dspu_save_dump.h_shipped7 0x20805000,
8 0x20805201,
9 0x20805402,
10 0x20805603,
11 0x20805804,
12 0x20805a05,
13 0x20805c06,
14 0x20805e07,
15 0x20806008,
16 0x2080620
[all...]
/linux/Documentation/devicetree/bindings/usb/
H A Dnxp,isp1760.yaml61 reg = <0x40200000 0x100000>;
/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa2xx.dtsi64 reg = <0x40d00000 0xd0>;
69 #address-cells = <0x1>;
70 #size-cells = <0x1>;
71 reg = <0x40e00000 0x10000>;
73 #gpio-cells = <0x2>;
77 #interrupt-cells = <0x2>;
81 reg = <0x40e00000 0x
[all...]
/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie-sa8775p.yaml101 reg = <0x0 0x01c00000 0x0 0x3000>,
102 <0x0 0x40000000 0x0 0xf20>,
103 <0x0 0x40000f2
[all...]
H A Dqcom,pcie-sc7280.yaml97 reg = <0 0x01c08000 0 0x3000>,
98 <0 0x40000000 0 0xf1d>,
99 <0 0x40000f2
[all...]
/linux/arch/arm64/boot/dts/qcom/
H A Dsa8540p-ride.dts34 regulators-0 {
162 pinctrl-0 = <&ethernet0_default>;
169 #size-cells = <0>;
173 compatible = "ethernet-phy-id0141.0dd4";
174 reg = <0x8>;
188 /* Set MODE[2:0] to RGMII_SGMII */
189 <0x12 0x14 0xfff8 0x
[all...]
H A Dipq5424.dtsi23 #clock-cells = <0>;
28 #clock-cells = <0>;
34 #size-cells = <0>;
36 cpu0: cpu@0 {
39 reg = <0x0>;
60 reg = <0x100>;
75 reg = <0x200>;
90 reg = <0x300>;
105 qcom,dload-mode = <&tcsr 0x25100>;
112 reg = <0x
[all...]
H A Dsar2130p.dtsi34 #clock-cells = <0>;
40 #clock-cells = <0>;
47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0x0 0x0>;
53 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x10
[all...]
/linux/arch/arm/boot/dts/arm/
H A Dmps2.dtsi53 #clock-cells = <0>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
71 #clock-cells = <0>;
77 #clock-cells = <0>;
84 #clock-cells = <0>;
92 #clock-cells = <0>;
100 #clock-cells = <0>;
113 ranges = <0 0x4000000
[all...]
/linux/arch/arm/mach-pxa/
H A Ddevices.c52 [0] = {
53 .start = 0x41100000,
54 .end = 0x41100fff,
69 .id = 0, in pxa_set_mci_info()
74 .dma_mask = 0xffffffffUL, in pxa_set_mci_info()
91 [0] = {
92 .start = 0x40600000,
93 .end = 0x4060ffff,
103 static u64 udc_dma_mask = ~(u32)0;
128 [0]
[all...]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-ipq4019.dtsi21 #address-cells = <0x1>;
22 #size-cells = <0x1>;
26 reg = <0x87e00000 0x080000>;
31 reg = <0x87e80000 0x180000>;
45 #size-cells = <0>;
46 cpu@0 {
53 reg = <0x0>;
55 clock-frequency = <0>;
[all...]
H A Dqcom-sdx65.dtsi20 qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>;
25 reg = <0 0>;
33 #clock-cells = <0>;
40 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #size-cells = <0>;
54 cpu0: cpu@0 {
[all...]

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