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/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Ddiu.txt20 reg = <0x2c000 100>;
28 reg = <0x2100 0x100>;
29 interrupts = <64 0x8>;
/linux/Documentation/devicetree/bindings/slimbus/
H A Dqcom,slim-ngd.yaml32 const: 0
49 "^slim@[0-9a-f]+$":
79 reg = <0x171c0000 0x2c000>;
84 iommus = <&apps_smmu 0x1806 0x0>;
86 #size-cells = <0>;
91 #size-cells = <0>;
93 codec@1,0 {
95 reg = <1 0>;
104 #clock-cells = <0>;
/linux/arch/powerpc/boot/dts/fsl/
H A Db4si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
71 reg = <0 0 0 0 0>;
72 interrupts = <20 2 0 0>;
[all …]
H A Dt2081si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
67 reg = <0 0 0 0 0>;
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dqcom,ipa.yaml222 qcom,local-pid = <0>;
244 iommus = <&apps_smmu 0x440 0x0>,
245 <&apps_smmu 0x442 0x0>;
246 reg = <0x1e40000 0x7000>,
247 <0x1e47000 0x2000>,
248 <0x1e04000 0x2c000>;
255 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
266 <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
267 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
268 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
[all …]
/linux/arch/powerpc/boot/dts/
H A Dmpc8308rdb.dts26 #size-cells = <0>;
28 PowerPC,8308@0 {
30 reg = <0x0>;
35 timebase-frequency = <0>; // from bootloader
36 bus-frequency = <0>; // from bootloader
37 clock-frequency = <0>; // from bootloader
43 reg = <0x00000000 0x08000000>; // 128MB at 0
50 reg = <0xe0005000 0x1000>;
51 interrupts = <77 0x8>;
57 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
H A Dmpc8308_p1m.dts25 #size-cells = <0>;
27 PowerPC,8308@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
42 reg = <0x00000000 0x08000000>; // 128MB at 0
49 reg = <0xe0005000 0x1000>;
50 interrupts = <77 0x8>;
53 ranges = <0x0 0x0 0xfc000000 0x04000000
[all …]
/linux/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_regs_cn9k_pf.h12 #define CN93_RST_BOOT 0x000087E006001600ULL
13 #define CN93_RST_CORE_DOMAIN_W1S 0x000087E006001820ULL
14 #define CN93_RST_CORE_DOMAIN_W1C 0x000087E006001828ULL
16 #define CN93_CONFIG_XPANSION_BAR 0x38
17 #define CN93_CONFIG_PCIE_CAP 0x70
18 #define CN93_CONFIG_PCIE_DEVCAP 0x74
19 #define CN93_CONFIG_PCIE_DEVCTL 0x78
20 #define CN93_CONFIG_PCIE_LINKCAP 0x7C
21 #define CN93_CONFIG_PCIE_LINKCTL 0x80
22 #define CN93_CONFIG_PCIE_SLOTCAP 0x84
[all …]
H A Doctep_regs_cnxk_pf.h12 #define CNXK_RST_BOOT 0x000087E006001600ULL
13 #define CNXK_RST_CHIP_DOMAIN_W1S 0x000087E006001810ULL
14 #define CNXK_RST_CORE_DOMAIN_W1S 0x000087E006001820ULL
15 #define CNXK_RST_CORE_DOMAIN_W1C 0x000087E006001828ULL
17 #define CNXK_CONFIG_XPANSION_BAR 0x38
18 #define CNXK_CONFIG_PCIE_CAP 0x70
19 #define CNXK_CONFIG_PCIE_DEVCAP 0x74
20 #define CNXK_CONFIG_PCIE_DEVCTL 0x78
21 #define CNXK_CONFIG_PCIE_LINKCAP 0x7C
22 #define CNXK_CONFIG_PCIE_LINKCTL 0x80
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_9_1_sar2130p.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
32 .base = 0x15000, .len = 0x290,
36 .base = 0x16000, .len = 0x290,
40 .base = 0x17000, .len = 0x290,
44 .base = 0x18000, .len = 0x290,
48 .base = 0x19000, .len = 0x290,
52 .base = 0x1a000, .len = 0x290,
60 .base = 0x4000, .len = 0x344,
[all …]
H A Ddpu_9_0_sm8550.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
32 .base = 0x15000, .len = 0x290,
36 .base = 0x16000, .len = 0x290,
40 .base = 0x17000, .len = 0x290,
44 .base = 0x18000, .len = 0x290,
48 .base = 0x19000, .len = 0x290,
52 .base = 0x1a000, .len = 0x290,
60 .base = 0x4000, .len = 0x344,
[all …]
H A Ddpu_10_0_sm8650.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
32 .base = 0x15000, .len = 0x1000,
36 .base = 0x16000, .len = 0x1000,
40 .base = 0x17000, .len = 0x1000,
44 .base = 0x18000, .len = 0x1000,
48 .base = 0x19000, .len = 0x1000,
52 .base = 0x1a000, .len = 0x1000,
60 .base = 0x4000, .len = 0x344,
[all …]
H A Ddpu_9_2_x1e80100.h11 .max_mixer_blendstages = 0xb,
22 .base = 0, .len = 0x494,
24 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
31 .base = 0x15000, .len = 0x290,
35 .base = 0x16000, .len = 0x290,
39 .base = 0x17000, .len = 0x290,
43 .base = 0x18000, .len = 0x290,
47 .base = 0x19000, .len = 0x290,
51 .base = 0x1a000, .len = 0x290,
59 .base = 0x4000, .len = 0x344,
[all …]
H A Ddpu_12_0_sm8750.h13 .max_mixer_blendstages = 0xb,
24 .base = 0, .len = 0x494,
26 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
33 .base = 0x15000, .len = 0x1000,
37 .base = 0x16000, .len = 0x1000,
41 .base = 0x17000, .len = 0x1000,
45 .base = 0x18000, .len = 0x1000,
49 .base = 0x19000, .len = 0x1000,
53 .base = 0x1a000, .len = 0x1000,
61 .base = 0x4000, .len = 0x344,
[all …]
/linux/drivers/gpu/drm/lima/
H A Dlima_device.c52 LIMA_IP_DESC(pmu, false, false, 0x02000, 0x02000, pmu, "pmu"),
53 LIMA_IP_DESC(l2_cache0, true, true, 0x01000, 0x10000, l2_cache, NULL),
54 LIMA_IP_DESC(l2_cache1, false, true, -1, 0x01000, l2_cache, NULL),
55 LIMA_IP_DESC(l2_cache2, false, false, -1, 0x11000, l2_cache, NULL),
56 LIMA_IP_DESC(gp, true, true, 0x00000, 0x00000, gp, "gp"),
57 LIMA_IP_DESC(pp0, true, true, 0x08000, 0x08000, pp, "pp0"),
58 LIMA_IP_DESC(pp1, false, false, 0x0A000, 0x0A000, pp, "pp1"),
59 LIMA_IP_DESC(pp2, false, false, 0x0C000, 0x0C000, pp, "pp2"),
60 LIMA_IP_DESC(pp3, false, false, 0x0E000, 0x0E000, pp, "pp3"),
61 LIMA_IP_DESC(pp4, false, false, -1, 0x28000, pp, "pp4"),
[all …]
/linux/drivers/rapidio/devices/
H A Dtsi721.h13 DBG_NONE = 0,
14 DBG_INIT = BIT(0), /* driver init */
26 DBG_ALL = ~0,
36 } while (0)
53 #define DEFAULT_HOPCOUNT 0xff
54 #define DEFAULT_DESTID 0xff
57 #define PCI_DEVICE_ID_TSI721 0x80ab
59 #define BAR_0 0
67 #define TSI721_MAINT_WIN 0 /* Window for outbound maintenance requests */
68 #define IDB_QUEUE 0 /* Inbound Doorbell Queue to use */
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dregs.h6 #define MT_HW_REV 0x1000
7 #define MT_HW_CHIPID 0x1008
8 #define MT_TOP_MISC2 0x1134
10 #define MT_MCU_BASE 0x2000
13 #define MT_MCU_PCIE_REMAP_1 MT_MCU(0x500)
14 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
17 #define MT_MCU_PCIE_REMAP_2 MT_MCU(0x504)
18 #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0)
21 #define MT_HIF_BASE 0x4000
24 #define MT_INT_SOURCE_CSR MT_HIF(0x200)
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dqcs615.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0x0 0x0>;
48 reg = <0x0 0x100>;
67 reg = <0x0 0x200>;
86 reg = <0x0 0x300>;
105 reg = <0x0 0x400>;
124 reg = <0x0 0x500>;
143 reg = <0x0 0x600>;
163 reg = <0x0 0x700>;
[all …]
H A Dsdm845.dtsi79 #clock-cells = <0>;
86 #clock-cells = <0>;
93 #size-cells = <0>;
95 cpu0: cpu@0 {
98 reg = <0x0 0x0>;
99 clocks = <&cpufreq_hw 0>;
103 qcom,freq-domain = <&cpufreq_hw 0>;
127 reg = <0x0 0x100>;
128 clocks = <&cpufreq_hw 0>;
132 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/linux/drivers/interconnect/qcom/
H A Dsm8650.c29 .port_offsets = { 0xc000 },
31 .urg_fwd = 0,
32 .prio_fwd_disable = 0,
47 .port_offsets = { 0xd000 },
49 .urg_fwd = 0,
50 .prio_fwd_disable = 0,
74 .port_offsets = { 0xe000 },
76 .urg_fwd = 0,
77 .prio_fwd_disable = 0,
92 .port_offsets = { 0xf000 },
[all …]
H A Dmilos.c142 .port_offsets = { 0xc000 },
144 .urg_fwd = 0,
159 .port_offsets = { 0xf200 },
161 .urg_fwd = 0,
176 .port_offsets = { 0x10000 },
178 .urg_fwd = 0,
193 .port_offsets = { 0x14000 },
195 .urg_fwd = 0,
210 .port_offsets = { 0x12000 },
212 .urg_fwd = 0,
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-ipq5424.c55 .offset = 0x20000,
58 .enable_reg = 0xb000,
59 .enable_mask = BIT(0),
83 .offset = 0x21000,
86 .enable_reg = 0xb000,
98 { 0x1, 2 },
103 .offset = 0x21000,
118 .offset = 0x22000,
121 .enable_reg = 0xb000,
144 { P_XO, 0 },
[all …]
H A Dgcc-msm8916.c45 .l_reg = 0x21004,
46 .m_reg = 0x21008,
47 .n_reg = 0x2100c,
48 .config_reg = 0x21010,
49 .mode_reg = 0x21000,
50 .status_reg = 0x2101c,
63 .enable_reg = 0x45000,
64 .enable_mask = BIT(0),
76 .l_reg = 0x20004,
77 .m_reg = 0x20008,
[all …]
H A Dgcc-msm8996.c49 .offset = 0x00000,
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
79 .offset = 0x00000,
94 .enable_reg = 0x5200c,
95 .enable_mask = BIT(0),
111 .enable_reg = 0x5200c,
126 .offset = 0x77000,
129 .enable_reg = 0x52000,
143 .offset = 0x77000,
[all …]
H A Dgcc-ipq5332.c53 .offset = 0x20000,
56 .enable_reg = 0xb000,
57 .enable_mask = BIT(0),
80 .offset = 0x20000,
93 .offset = 0x21000,
96 .enable_reg = 0xb000,
108 .offset = 0x21000,
121 .offset = 0x22000,
124 .enable_reg = 0xb000,
136 .offset = 0x22000,
[all …]

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