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/linux/arch/arm/boot/dts/marvell/
H A Darmada-385-linksys-caiman.dts18 wan_amber@0 {
20 reg = <0x0>;
25 reg = <0x1>;
30 reg = <0x2>;
35 reg = <0x3>;
40 reg = <0x5>;
45 reg = <0x6>;
50 reg = <0x7>;
55 reg = <0x8>;
60 reg = <0x
[all...]
H A Darmada-385-linksys-shelby.dts18 wan_amber@0 {
20 reg = <0x0>;
25 reg = <0x1>;
30 reg = <0x2>;
35 reg = <0x3>;
40 reg = <0x5>;
45 reg = <0x6>;
50 reg = <0x7>;
55 reg = <0x8>;
60 reg = <0x
[all...]
H A Darmada-385-linksys-cobra.dts18 wan_amber@0 {
20 reg = <0x0>;
25 reg = <0x1>;
30 reg = <0x2>;
35 reg = <0x3>;
40 reg = <0x5>;
45 reg = <0x6>;
50 reg = <0x7>;
55 reg = <0x8>;
60 reg = <0x
[all...]
/linux/Documentation/devicetree/bindings/watchdog/
H A Dti,rti-wdt.yaml42 PON_REASON_SOF_NUM(0xBBBBCCCC), PON_REASON_MAGIC_NUM(0xDDDDDDDD),
43 and PON_REASON_EOF_NUM(0xCCCCBBBB), are pre-stored at the first
48 specific memory address(0xa220000) should be set. More please
66 * starting from 0xa2200000 by RTI Watchdog Firmware, then make it
72 * reg = <0x00 0xa2200000 0x00 0x1000>;
81 reg = <0x220000
[all...]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dbrcm,bcm2835-gpio.txt17 - bit 0 specifies polarity (0 for normal, 1 for inverted)
26 bits[3:0] trigger type and level flags:
66 are the integer GPIO IDs; 0==GPIO0, 1==GPIO1, ... 53==GPIO53.
70 0: GPIO in
79 0: none
91 reg = <0x2200000 0xb4>;
/linux/Documentation/devicetree/bindings/gpio/
H A Dnvidia,tegra186-gpio.yaml125 - Bit 0 specifies polarity
126 - 0: Active-high (normal).
140 - Bits [3:0] indicate trigger type and level:
193 reg = <0x2200000 0x10000>,
194 <0x2210000 0x10000>;
195 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>,
196 <0 5
[all...]
/linux/arch/mips/boot/dts/mobileye/
H A Deyeq5.dtsi15 #size-cells = <0>;
16 cpu@0 {
19 reg = <0>;
34 reg = <0x8 0x04000000 0x0 0x1000000>;
37 reg = <0x8 0x05000000 0x
[all...]
/linux/drivers/net/ethernet/microchip/sparx5/lan969x/
H A Dlan969x.c13 { TARGET_CPU, 0xc0000, 0 }, /* 0xe00c0000 */
14 { TARGET_FDMA, 0xc0400, 0 }, /* 0xe00c0400 */
15 { TARGET_GCB, 0x2010000, 1 }, /* 0xe2010000 */
16 { TARGET_QS, 0x2030000, 1 }, /* 0xe203000
[all...]
/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-sm-k26-revA.dts50 memory@0 {
52 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
61 reg = <0x
[all...]
/linux/arch/openrisc/kernel/
H A Dtraps.c61 if (i == 0) in print_data()
85 in_kernel = 0; in show_registers()
91 0L, regs->gpr[1], regs->gpr[2], regs->gpr[3]); in show_registers()
160 pr_emerg("\n%s#: %04lx\n", str, err & 0xffff); in die()
176 pr_emerg("Unable to handle exception at EA =0x%x, vector 0x%x", in unhandled_exception()
208 pr_emerg("KERNEL: Illegal fpe exception 0x%.8lx\n", regs->pc); in do_fpe_trap()
218 pr_emerg("KERNEL: Illegal trap exception 0x%.8lx\n", regs->pc); in do_trap()
229 pr_emerg("KERNEL: Unaligned Access 0x%.8lx\n", address); in do_unaligned_access()
241 pr_emerg("KERNEL: Bus error (SIGBUS) 0 in do_bus_fault()
[all...]
/linux/arch/arm64/boot/dts/qcom/
H A Dsdm670-google-sargo.dts45 reg = <0 0x9c000000 0 (1080 * 2220 * 4)>;
58 pinctrl-0 = <&vol_up_pin>;
72 reg = <0 0x8b000000 0 0x9800000>;
77 reg = <0 0x9480000
[all...]
H A Dmsm8994.dtsi29 #clock-cells = <0>;
36 #clock-cells = <0>;
44 #size-cells = <0>;
46 cpu0: cpu@0 {
49 reg = <0x0 0x0>;
62 reg = <0x0 0x1>;
70 reg = <0x0 0x
[all...]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j7200-main.dtsi10 #clock-cells = <0>;
18 reg = <0x00 0x70000000 0x00 0x100000>;
21 ranges = <0x00 0x00 0x70000000 0x100000>;
23 atf-sram@0 {
[all...]
H A Dk3-j721s2-main.dtsi13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x0 0x70000000 0x0 0x400000>;
25 ranges = <0x0 0x0 0x70000000 0x40000
[all...]
H A Dk3-j784s4-j742s2-main-common.dtsi16 #clock-cells = <0>;
30 reg = <0x00 0x70000000 0x00 0x800000>;
33 ranges = <0x00 0x00 0x70000000 0x800000>;
35 atf-sram@0 {
[all...]
H A Dk3-j721e-main.dtsi15 #clock-cells = <0>;
17 clock-frequency = <0>;
21 #clock-cells = <0>;
23 clock-frequency = <0>;
30 reg = <0x0 0x70000000 0x0 0x800000>;
33 ranges = <0x0 0x
[all...]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra186.dtsi20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x1000>;
27 reg = <0x0 0x220000
[all...]
H A Dtegra194.dtsi20 bus@0 {
25 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
29 reg = <0x0 0x00100000 0x
[all...]
/linux/drivers/scsi/qla2xxx/
H A Dqla_nx.c15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
16 ((addr >> 25) & 0x3ff))
17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
18 ((addr >> 25) & 0x3ff))
19 #define MS_WIN(addr) (addr & 0x0ffc0000)
20 #define QLA82XX_PCI_MN_2M (0)
21 #define QLA82XX_PCI_MS_2M (0x80000)
22 #define QLA82XX_PCI_OCM0_2M (0xc0000)
23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f80
[all...]
/linux/drivers/scsi/qla4xxx/
H A Dql4_nx.c18 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
19 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
20 #define MS_WIN(addr) (addr & 0x0ffc0000)
21 #define QLA82XX_PCI_MN_2M (0)
22 #define QLA82XX_PCI_MS_2M (0x80000)
23 #define QLA82XX_PCI_OCM0_2M (0xc0000)
24 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f80
[all...]