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/linux/arch/arm/mach-omap2/
H A Dprm54xx.h24 #define OMAP54XX_PRM_BASE 0x4ae06000
31 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
32 #define OMAP54XX_PRM_CKGEN_INST 0x0100
33 #define OMAP54XX_PRM_MPU_INST 0x0300
34 #define OMAP54XX_PRM_DSP_INST 0x0400
35 #define OMAP54XX_PRM_ABE_INST 0x0500
36 #define OMAP54XX_PRM_COREAON_INST 0x0600
37 #define OMAP54XX_PRM_CORE_INST 0x0700
38 #define OMAP54XX_PRM_IVA_INST 0x1200
39 #define OMAP54XX_PRM_CAM_INST 0x130
[all...]
H A Dprm7xx.h26 #define DRA7XX_PRM_BASE 0x4ae06000
33 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
34 #define DRA7XX_PRM_CKGEN_INST 0x0100
35 #define DRA7XX_PRM_MPU_INST 0x0300
36 #define DRA7XX_PRM_DSP1_INST 0x0400
37 #define DRA7XX_PRM_IPU_INST 0x0500
38 #define DRA7XX_PRM_COREAON_INST 0x0628
39 #define DRA7XX_PRM_CORE_INST 0x0700
40 #define DRA7XX_PRM_IVA_INST 0x0f00
41 #define DRA7XX_PRM_CAM_INST 0x100
[all...]
H A Dprm44xx.h28 #define OMAP4430_PRM_BASE 0x4a306000
35 #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
36 #define OMAP4430_PRM_CKGEN_INST 0x0100
37 #define OMAP4430_PRM_MPU_INST 0x0300
38 #define OMAP4430_PRM_TESLA_INST 0x0400
39 #define OMAP4430_PRM_ABE_INST 0x0500
40 #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
41 #define OMAP4430_PRM_CORE_INST 0x0700
42 #define OMAP4430_PRM_IVAHD_INST 0x0f00
43 #define OMAP4430_PRM_CAM_INST 0x100
[all...]
/linux/drivers/media/pci/mgb4/
H A Dmgb4_cmt.c19 {0x1208, 0x0000, 0x171C, 0x0000, 0x1E38, 0x0000, 0x11C7, 0x0000, 0x1041, 0x01B
[all...]
/linux/arch/s390/include/asm/
H A Dlowcore.h23 #define LOWCORE_ALT_ADDRESS _AC(0x70000, UL)
32 __u8 pad_0x0000[0x0014-0x0000]; /* 0x0000 */
33 __u32 ipl_parmblock_ptr; /* 0x0014 */
34 __u8 pad_0x0018[0x0080-0x0018]; /* 0x0018 */
35 __u32 ext_params; /* 0x0080 */
38 __u16 ext_cpu_addr; /* 0x008
[all...]
/linux/drivers/regulator/
H A Dslg51000-regulator.h14 #define SLG51000_SYSCTL_PATN_ID_B0 0x1105
15 #define SLG51000_SYSCTL_PATN_ID_B1 0x1106
16 #define SLG51000_SYSCTL_PATN_ID_B2 0x1107
17 #define SLG51000_SYSCTL_SYS_CONF_A 0x1109
18 #define SLG51000_SYSCTL_SYS_CONF_D 0x110c
19 #define SLG51000_SYSCTL_MATRIX_CONF_A 0x110d
20 #define SLG51000_SYSCTL_MATRIX_CONF_B 0x110e
21 #define SLG51000_SYSCTL_REFGEN_CONF_C 0x1111
22 #define SLG51000_SYSCTL_UVLO_CONF_A 0x1112
23 #define SLG51000_SYSCTL_FAULT_LOG1 0x111
[all...]
/linux/drivers/video/fbdev/
H A Dcarminefb_regs.h5 #define CARMINE_OVERLAY_EXT_MODE (0x00000002)
6 #define CARMINE_GRAPH_REG (0x00000000)
7 #define CARMINE_DISP0_REG (0x00100000)
8 #define CARMINE_DISP1_REG (0x00140000)
9 #define CARMINE_WB_REG (0x00180000)
10 #define CARMINE_DCTL_REG (0x00300000)
11 #define CARMINE_CTL_REG (0x00400000)
12 #define CARMINE_WINDOW_MODE (0x00000001)
19 #define CARMINE_EXT_CMODE_DIRECT24_RGBA (0xC0000000)
20 #define CARMINE_DCTL_REG_MODE_ADD (0x0
[all...]
/linux/Documentation/devicetree/bindings/media/
H A Dqcom,x1e80100-camss.yaml121 vdd-csiphy-0p8-supply:
136 "^port@[0-3]$":
174 - vdd-csiphy-0p8-supply
196 reg = <0 0x0acb7000 0 0x2000>,
197 <0 0x0acb9000 0
[all...]
/linux/drivers/ufs/host/
H A Dufs-qcom.h13 #define MPHY_TX_FSM_STATE 0x41
14 #define TX_FSM_HIBERN8 0x1
22 #define UFS_HW_VER_STEP_MASK GENMASK(15, 0)
28 #define PA_VS_CLK_CFG_REG 0x9004
29 #define PA_VS_CLK_CFG_REG_MASK GENMASK(8, 0)
32 #define DL_VS_CLK_CFG 0xA00B
33 #define DL_VS_CLK_CFG_MASK GENMASK(9, 0)
38 REG_UFS_SYS1CLK_1US = 0xC0,
39 REG_UFS_TX_SYMBOL_CLK_NS_US = 0xC4,
40 REG_UFS_LOCAL_PORT_ID_REG = 0xC
[all...]
/linux/Documentation/devicetree/bindings/net/wireless/
H A Dqcom,ath10k.yaml136 enum: [0, 1]
303 reg = <0x18800000 0x800000>;
320 iommus = <&anoc2_smmu 0x1900>,
321 <&anoc2_smmu 0x1901>;
330 iommus = <&apps_smmu 0x1c02 0x1>;
340 reg = <0xa000000 0x20000
[all...]
/linux/arch/mips/boot/dts/loongson/
H A Dloongson64-2k1000.dtsi15 #size-cells = <0>;
17 cpu0: cpu@0 {
20 reg = <0x0>;
27 #clock-cells = <0>;
33 #address-cells = <0>;
43 ranges = <0 0x10000000 0 0x10000000 0
[all...]
H A Dls7a-pch.dtsi8 ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
9 0 0x20000000 0 0x2000000
[all...]
/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x100
[all...]
/linux/drivers/net/ethernet/hisilicon/hns3/hns3_common/
H A Dhclge_comm_cmd.h10 #define HCLGE_COMM_CMD_FLAG_IN BIT(0)
18 #define HCLGE_COMM_LINK_EVENT_REPORT_EN_B 0
28 #define HCLGE_COMM_TYPE_CRQ 0
34 #define HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG 0x27000
35 #define HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG 0x27004
36 #define HCLGE_COMM_NIC_CSQ_DEPTH_REG 0x27008
37 #define HCLGE_COMM_NIC_CSQ_TAIL_REG 0x27010
38 #define HCLGE_COMM_NIC_CSQ_HEAD_REG 0x27014
39 #define HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG 0x27018
40 #define HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG 0x2701
[all...]
/linux/drivers/media/rc/keymaps/
H A Drc-hauppauge.c27 * Keycodes start with address = 0x1e
30 { 0x1e3b, KEY_SELECT }, /* GO / house symbol */
31 { 0x1e3d, KEY_POWER2 }, /* system power (green button) */
33 { 0x1e1c, KEY_TV },
34 { 0x1e18, KEY_VIDEO }, /* Videos */
35 { 0x1e19, KEY_AUDIO }, /* Music */
36 { 0x1e1a, KEY_CAMERA }, /* Pictures */
38 { 0x1e1b, KEY_EPG }, /* Guide */
39 { 0x1e0c, KEY_RADIO },
41 { 0x1e1
[all...]
/linux/drivers/media/i2c/
H A Dmsp3400-kthreads.c28 { 0x0000, 0, 0, "could not detect sound standard", V4L2_STD_ALL },
29 { 0x0001, 0, 0, "autodetect start", V4L2_STD_ALL },
30 { 0x0002, MSP_CARRIER(4.5), MSP_CARRIER(4.72),
32 { 0x0003, MSP_CARRIER(5.5), MSP_CARRIER(5.7421875),
34 { 0x0004, MSP_CARRIER(6.5), MSP_CARRIER(6.2578125),
36 { 0x000
[all...]
/linux/drivers/comedi/drivers/
H A Dni_atmio.c87 RANGE_ext(0, 1)
96 .isapnp_id = 0x0000, /* XXX unknown */
98 .ai_maxdata = 0x0fff,
103 .ao_maxdata = 0x0fff,
111 .isapnp_id = 0x1900,
113 .ai_maxdata = 0x0fff,
118 .ao_maxdata = 0x0fff,
126 .isapnp_id = 0x2400,
128 .ai_maxdata = 0x0ff
[all...]
/linux/drivers/bus/
H A Domap_l3_noc.h16 #define CUSTOM_ERROR 0x2
17 #define STANDARD_ERROR 0x0
18 #define INBAND_ERROR 0x0
19 #define L3_APPLICATION_ERROR 0x0
20 #define L3_DEBUG_ERROR 0x1
23 #define L3_TARG_STDERRLOG_MAIN 0x48
24 #define L3_TARG_STDERRLOG_HDR 0x4c
25 #define L3_TARG_STDERRLOG_MSTADDR 0x50
26 #define L3_TARG_STDERRLOG_INFO 0x58
27 #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5
[all...]
/linux/drivers/gpu/drm/loongson/
H A Dlsdc_regs.h24 #define LS7A1000_PIXPLL0_REG 0x04B0
25 #define LS7A1000_PIXPLL1_REG 0x04C0
28 #define LS7A1000_PLL_GFX_REG 0x0490
30 #define LS7A1000_CONF_REG_BASE 0x10010000
34 #define LS7A2000_PIXPLL0_REG 0x04B0
35 #define LS7A2000_PIXPLL1_REG 0x04C0
38 #define LS7A2000_PLL_GFX_REG 0x0490
40 #define LS7A2000_CONF_REG_BASE 0x10010000
43 #define CFG_PIX_FMT_MASK GENMASK(2, 0)
46 LSDC_PF_NONE = 0,
[all...]
/linux/drivers/net/wireless/realtek/rtlwifi/
H A Ddebug.c80 int max = 0xff; in rtl_debug_get_mac_page()
82 for (n = 0; n <= max; ) { in rtl_debug_get_mac_page()
84 for (i = 0; i < 4 && n <= max; i++, n += 4) in rtl_debug_get_mac_page()
89 return 0; in rtl_debug_get_mac_page()
98 RTL_DEBUG_IMPL_MAC_SERIES(0, 0x0000);
99 RTL_DEBUG_IMPL_MAC_SERIES(1, 0x0100);
100 RTL_DEBUG_IMPL_MAC_SERIES(2, 0x0200);
101 RTL_DEBUG_IMPL_MAC_SERIES(3, 0x0300);
102 RTL_DEBUG_IMPL_MAC_SERIES(4, 0x040
[all...]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/
H A Dg98.fuc0s23 ctx_dma_query: .b32 0
24 ctx_dma_src: .b32 0
25 ctx_dma_dst: .b32 0
27 ctx_query_address_high: .b32 0
28 ctx_query_address_low: .b32 0
29 ctx_query_counter: .b32 0
30 ctx_cond_address_high: .b32 0
31 ctx_cond_address_low: .b32 0
32 ctx_cond_off: .b32 0
33 ctx_src_address_high: .b32 0
[all...]
/linux/arch/loongarch/boot/dts/
H A Dloongson-2k1000.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg= <0x0>;
30 reg = <0x1>;
37 #clock-cells = <0>;
49 i2c-gpio-0 {
51 scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
55 #size-cells = <0>;
66 #size-cells = <0>;
74 thermal-sensors = <&tsensor 0>;
[all...]
/linux/drivers/clk/imx/
H A Dclk-imx93.c20 #define PLAT_IMX93 BIT(0)
65 { IMX93_CLK_A55_PERIPH, "a55_periph_root", 0x0000, FAST_SEL, CLK_IS_CRITICAL },
66 { IMX93_CLK_A55_MTR_BUS, "a55_mtr_bus_root", 0x0080, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
67 { IMX93_CLK_A55, "a55_alt_root", 0x0100, FAST_SEL, CLK_IS_CRITICAL },
68 { IMX93_CLK_M33, "m33_root", 0x0180, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
69 { IMX93_CLK_BUS_WAKEUP, "bus_wakeup_root", 0x0280, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
70 { IMX93_CLK_BUS_AON, "bus_aon_root", 0x0300, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
71 { IMX93_CLK_WAKEUP_AXI, "wakeup_axi_root", 0x0380, FAST_SEL, CLK_IS_CRITICAL },
72 { IMX93_CLK_SWO_TRACE, "swo_trace_root", 0x0400, LOW_SPEED_IO_SEL, },
73 { IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x048
[all...]
/linux/drivers/net/ethernet/amd/
H A Dariadne.h17 * Publication #16907, Rev. B, Amendment/0, May 1994
62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
63 #define CSR1 0x0100 /* - IADR[15:0] */
64 #define CSR2 0x0200 /* - IADR[23:16] */
65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
66 #define CSR4 0x0400 /* - Test and Features Control */
67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
[all...]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap54xx-clocks.dtsi9 #clock-cells = <0>;
16 #clock-cells = <0>;
21 reg = <0x0108>;
25 #clock-cells = <0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
44 reg = <0x0108>;
48 #clock-cells = <0>;
55 #clock-cells = <0>;
62 #clock-cells = <0>;
[all...]

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