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/linux/drivers/gpu/drm/ast/
H A Dast_2000.c40 static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff }; in ast_2000_set_def_ext_reg()
45 for (i = 0x81; i <= 0x9f; i++) in ast_2000_set_def_ext_reg()
46 ast_set_index_reg(ast, AST_IO_VGACRI, i, 0x00); in ast_2000_set_def_ext_reg()
49 index = 0xa0; in ast_2000_set_def_ext_reg()
50 while (*ext_reg_info != 0xff) { in ast_2000_set_def_ext_reg()
51 ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info); in ast_2000_set_def_ext_reg()
57 /* ast_set_index_reg-mask(ast, AST_IO_VGACRI, 0xa1, 0xff, 0x3); */ in ast_2000_set_def_ext_reg()
60 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01); in ast_2000_set_def_ext_reg()
61 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00); in ast_2000_set_def_ext_reg()
64 reg = 0x04; in ast_2000_set_def_ext_reg()
[all …]
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dmpc512x_lpbfifo.txt16 reg = <0x10100 0x50>;
17 interrupts = <7 0x8>;
/linux/Documentation/devicetree/bindings/mips/cavium/
H A Dciu3.txt24 #address-cells = <0>;
26 reg = <0x10100 0x00000000 0x0 0xb0000000>;
/linux/arch/arm64/boot/dts/apple/
H A Dt8112-j413.dts27 led-0 {
28 pwms = <&fpwm1 0 40000>;
45 wifi0: wifi@0,0 {
47 reg = <0x10000 0x0 0x0 0x0 0x0>;
54 bluetooth0: bluetooth@0,1 {
56 reg = <0x10100 0x0 0x0 0x0 0x0>;
67 reg = <0x3a>;
H A Dt8103-jxxx.dtsi27 framebuffer0: framebuffer@0 {
29 reg = <0 0 0 0>; /* To be filled by loader */
37 reg = <0x8 0 0x2 0>; /* To be filled by loader */
52 reg = <0x38>;
60 reg = <0x3f>;
74 wifi0: wifi@0,0 {
76 reg = <0x10000 0x0 0x0 0x0 0x0>;
82 bluetooth0: bluetooth@0,1 {
84 reg = <0x10100 0x0 0x0 0x0 0x0>;
H A Dt8112-j493.dts32 led-0 {
33 pwms = <&fpwm1 0 40000>;
58 dfr_mipi_out_panel: endpoint@0 {
59 reg = <0>;
67 #size-cells = <0>;
69 dfr_panel: panel@0 {
71 reg = <0>;
93 wifi0: wifi@0,0 {
95 reg = <0x10000 0x0 0x0 0x0 0x0>;
102 bluetooth0: bluetooth@0,1 {
[all …]
H A Dt600x-common.dtsi20 #size-cells = <0>;
63 cpu_e00: cpu@0 {
66 reg = <0x0 0x0>;
68 cpu-release-addr = <0 0>; /* To be filled by loader */
70 i-cache-size = <0x20000>;
71 d-cache-size = <0x10000>;
80 reg = <0x0 0x1>;
82 cpu-release-addr = <0 0>; /* To be filled by loader */
84 i-cache-size = <0x20000>;
85 d-cache-size = <0x10000>;
[all …]
/linux/arch/m68k/include/asm/
H A Dapollohw.h52 #define IO_BASE 0x80000000
62 #define SAU7_SIO01_PHYSADDR 0x10400
63 #define SAU7_SIO23_PHYSADDR 0x10500
64 #define SAU7_RTC_PHYSADDR 0x10900
65 #define SAU7_PICA 0x11000
66 #define SAU7_PICB 0x11100
67 #define SAU7_CPUCTRL 0x10100
68 #define SAU7_TIMER 0x010800
70 #define SAU8_SIO01_PHYSADDR 0x8400
71 #define SAU8_RTC_PHYSADDR 0x8900
[all …]
/linux/Documentation/devicetree/bindings/cpufreq/
H A Dapple,cluster-cpufreq.yaml43 const: 0
59 #size-cells = <0>;
61 cpu@0 {
64 reg = <0x0 0x0>;
72 reg = <0x0 0x10100>;
78 ecluster_opp: opp-table-0 {
116 reg = <0x2 0x10e20000 0 0x1000>;
117 #performance-domain-cells = <0>;
122 reg = <0x2 0x11e20000 0 0x1000>;
123 #performance-domain-cells = <0>;
/linux/drivers/net/ethernet/marvell/octeon_ep_vf/
H A Doctep_vf_regs_cn9k.h11 #define CN93_VF_CONFIG_XPANSION_BAR 0x38
12 #define CN93_VF_CONFIG_PCIE_CAP 0x70
13 #define CN93_VF_CONFIG_PCIE_DEVCAP 0x74
14 #define CN93_VF_CONFIG_PCIE_DEVCTL 0x78
15 #define CN93_VF_CONFIG_PCIE_LINKCAP 0x7C
16 #define CN93_VF_CONFIG_PCIE_LINKCTL 0x80
17 #define CN93_VF_CONFIG_PCIE_SLOTCAP 0x84
18 #define CN93_VF_CONFIG_PCIE_SLOTCTL 0x88
23 #define CN93_VF_SDP_R_IN_CONTROL_START 0x10000
24 #define CN93_VF_SDP_R_IN_ENABLE_START 0x10010
[all …]
H A Doctep_vf_regs_cnxk.h11 #define CNXK_VF_CONFIG_XPANSION_BAR 0x38
12 #define CNXK_VF_CONFIG_PCIE_CAP 0x70
13 #define CNXK_VF_CONFIG_PCIE_DEVCAP 0x74
14 #define CNXK_VF_CONFIG_PCIE_DEVCTL 0x78
15 #define CNXK_VF_CONFIG_PCIE_LINKCAP 0x7C
16 #define CNXK_VF_CONFIG_PCIE_LINKCTL 0x80
17 #define CNXK_VF_CONFIG_PCIE_SLOTCAP 0x84
18 #define CNXK_VF_CONFIG_PCIE_SLOTCTL 0x88
20 #define CNXK_VF_RING_OFFSET (0x1ULL << 17)
23 #define CNXK_VF_SDP_R_IN_CONTROL_START 0x10000
[all …]
/linux/Documentation/devicetree/bindings/arm/
H A Dcpus.yaml30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
48 and must be set to 0.
51 CPUID[11:0] register bits.
53 Bits [11:0] in the reg cell must be set to bits [11:0] in CPU ID register.
55 All other bits in the reg cell must be set to 0.
58 the CPU MPIDR[23:0] register bits.
60 Bits [23:0] in the reg cell must be set to bits [23:0] in MPIDR.
62 All other bits in the reg cell must be set to 0.
69 The first reg cell bits [7:0] must be set to bits [39:32] of
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Dorion5x.dtsi24 reg = <MBUS_ID(0xf0, 0x01) 0x1046C 0x4>;
25 ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>;
28 clocks = <&core_clk 0>;
34 reg = <MBUS_ID(0xf0, 0x01) 0x1045C 0x4>;
35 ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>;
38 clocks = <&core_clk 0>;
44 reg = <MBUS_ID(0xf0, 0x01) 0x10460 0x4>;
45 ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>;
48 clocks = <&core_clk 0>;
54 reg = <MBUS_ID(0xf0, 0x01) 0x10464 0x4>;
[all …]
H A Dkirkwood.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
37 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */
38 MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */
39 MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */
42 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
43 pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
48 cle = <0>;
52 reg = <MBUS_ID(0x01, 0x2f) 0 0x400>;
[all …]
/linux/arch/powerpc/boot/dts/
H A Dmpc5125twr.dts30 #size-cells = <0>;
32 PowerPC,5125@0 {
34 reg = <0>;
35 d-cache-line-size = <0x20>; // 32 bytes
36 i-cache-line-size = <0x20>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
47 reg = <0x00000000 0x10000000>; // 256MB at 0
52 reg = <0x30000000 0x08000>; // 32K at 0x30000000
57 #size-cells = <0>;
[all …]
H A Dmpc5121.dtsi26 #size-cells = <0>;
28 PowerPC,5121@0 {
30 reg = <0>;
31 d-cache-line-size = <0x20>; /* 32 bytes */
32 i-cache-line-size = <0x20>; /* 32 bytes */
33 d-cache-size = <0x8000>; /* L1, 32K */
34 i-cache-size = <0x8000>; /* L1, 32K */
43 reg = <0x00000000 0x10000000>; /* 256MB at 0 */
48 reg = <0x20000000 0x4000>;
49 interrupts = <66 0x8>;
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Dmorello.dtsi16 #clock-cells = <0>;
23 #clock-cells = <0>;
30 #size-cells = <0>;
32 cpu0: cpu@0 {
34 reg = <0x0 0x0>;
38 i-cache-size = <0x10000>;
41 d-cache-size = <0x10000>;
45 clocks = <&scmi_dvfs 0>;
51 cache-size = <0x100000>;
61 reg = <0x0 0x100>;
[all …]
H A Dfvp-base-revc.dts15 /memreserve/ 0x80000000 0x00010000;
45 #size-cells = <0>;
50 CPU_SLEEP_0: cpu-sleep-0 {
53 arm,psci-suspend-param = <0x0010000>;
60 CLUSTER_SLEEP_0: cluster-sleep-0 {
63 arm,psci-suspend-param = <0x1010000>;
71 cpu0: cpu@0 {
74 reg = <0x0 0x000>;
76 i-cache-size = <0x8000>;
79 d-cache-size = <0x8000>;
[all …]
/linux/drivers/rapidio/switches/
H A Didt_gen3.c18 #define RIO_EM_PW_STAT 0x40020
19 #define RIO_PW_CTL 0x40204
20 #define RIO_PW_CTL_PW_TMR 0xffffff00
21 #define RIO_PW_ROUTE 0x40208
23 #define RIO_EM_DEV_INT_EN 0x40030
25 #define RIO_PLM_SPx_IMP_SPEC_CTL(x) (0x10100 + (x)*0x100)
26 #define RIO_PLM_SPx_IMP_SPEC_CTL_SOFT_RST 0x02000000
28 #define RIO_PLM_SPx_PW_EN(x) (0x10118 + (x)*0x100)
29 #define RIO_PLM_SPx_PW_EN_OK2U 0x40000000
30 #define RIO_PLM_SPx_PW_EN_LINIT 0x10000000
[all …]
/linux/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_regs_cn9k_pf.h12 #define CN93_RST_BOOT 0x000087E006001600ULL
13 #define CN93_RST_CORE_DOMAIN_W1S 0x000087E006001820ULL
14 #define CN93_RST_CORE_DOMAIN_W1C 0x000087E006001828ULL
16 #define CN93_CONFIG_XPANSION_BAR 0x38
17 #define CN93_CONFIG_PCIE_CAP 0x70
18 #define CN93_CONFIG_PCIE_DEVCAP 0x74
19 #define CN93_CONFIG_PCIE_DEVCTL 0x78
20 #define CN93_CONFIG_PCIE_LINKCAP 0x7C
21 #define CN93_CONFIG_PCIE_LINKCTL 0x80
22 #define CN93_CONFIG_PCIE_SLOTCAP 0x84
[all …]
H A Doctep_regs_cnxk_pf.h12 #define CNXK_RST_BOOT 0x000087E006001600ULL
13 #define CNXK_RST_CHIP_DOMAIN_W1S 0x000087E006001810ULL
14 #define CNXK_RST_CORE_DOMAIN_W1S 0x000087E006001820ULL
15 #define CNXK_RST_CORE_DOMAIN_W1C 0x000087E006001828ULL
17 #define CNXK_CONFIG_XPANSION_BAR 0x38
18 #define CNXK_CONFIG_PCIE_CAP 0x70
19 #define CNXK_CONFIG_PCIE_DEVCAP 0x74
20 #define CNXK_CONFIG_PCIE_DEVCTL 0x78
21 #define CNXK_CONFIG_PCIE_LINKCAP 0x7C
22 #define CNXK_CONFIG_PCIE_LINKCTL 0x80
[all …]
/linux/drivers/crypto/marvell/octeontx2/
H A Dotx2_cpt_hw_types.h11 #define OTX2_CPT_PCI_PF_DEVICE_ID 0xA0FD
12 #define OTX2_CPT_PCI_VF_DEVICE_ID 0xA0FE
13 #define CN10K_CPT_PCI_PF_DEVICE_ID 0xA0F2
14 #define CN10K_CPT_PCI_VF_DEVICE_ID 0xA0F3
16 #define CPT_PCI_SUBSYS_DEVID_CN10K_A 0xB900
17 #define CPT_PCI_SUBSYS_DEVID_CN10K_B 0xBD00
32 #define OTX2_CPT_VF_INTR_MBOX_MASK BIT(0)
33 #define CN10K_CPT_VF_MBOX_REGION (0xC0000)
39 #define OTX2_CPT_PF_CONSTANTS (0x0)
40 #define OTX2_CPT_PF_RESET (0x100)
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/pcie/
H A Dpcie_6_1_0_offset.h28 // base address: 0x11a08000
29 …O_HWDID 0x2270800
30 …e regDXIO_HWDID_BASE_IDX 0
31 …O_LINKAGE_LANEGRP 0x2270802
32 …e regDXIO_LINKAGE_LANEGRP_BASE_IDX 0
33 …O_LINKAGE_KPDMX 0x2270803
34 …e regDXIO_LINKAGE_KPDMX_BASE_IDX 0
35 …O_LINKAGE_KPMX 0x2270804
36 …O_LINKAGE_KPFIFO 0x2270805
37 …O_LINKAGE_KPNP 0x2270806
[all …]
/linux/Documentation/devicetree/bindings/cpu/
H A Didle-states.yaml102 between 0 and infinite time, until a wake-up event occurs.
127 wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
167 0| 1 time(ms)
172 The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
444 #size-cells = <0>;
447 cpu@0 {
450 reg = <0x0 0x0>;
459 reg = <0x0 0x1>;
468 reg = <0x0 0x100>;
477 reg = <0x0 0x101>;
[all …]
/linux/arch/arm64/boot/dts/xilinx/
H A Dversal-net.dtsi23 bootscr-address = /bits/ 64 <0x20000000>;
29 #size-cells = <0>;
100 cpu0: cpu@0 {
104 reg = <0>;
112 reg = <0x100>;
120 reg = <0x200>;
128 reg = <0x300>;
136 reg = <0x10000>;
144 reg = <0x10100>;
152 reg = <0x10200>;
[all …]

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