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/linux/Documentation/devicetree/bindings/misc/
H A Dqcom,fastrpc.yaml65 const: 0
68 "(compute-)?cb@[0-9]*$":
127 #size-cells = <0>;
132 iommus = <&apps_smmu 0x0541 0x0>;
138 iommus = <&apps_smmu 0x0542 0x0>;
144 iommus = <&apps_smmu 0x0543 0x0>;
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h27 // base address: 0x1fb00
28 …UVD_PGFSM_CONFIG 0x00c0
30 …UVD_PGFSM_STATUS 0x00c1
32 …UVD_POWER_STATUS 0x00c4
34 …CC_UVD_HARVESTING 0x00c7
36 …UVD_DPG_LMA_CTL 0x00d1
38 …UVD_DPG_LMA_DATA 0x00d2
40 …UVD_DPG_LMA_MASK 0x00d3
42 …UVD_DPG_PAUSE 0x00d4
44 …UVD_SCRATCH1 0x00d5
[all …]
H A Dvcn_4_0_0_offset.h29 // base address: 0x1fb00
30 …UVD_TOP_CTRL 0x00c0
32 …UVD_CGC_GATE 0x00c1
34 …UVD_CGC_CTRL 0x00c2
36 …AVM_SUVD_CGC_GATE 0x00c4
38 …CDEFE_SUVD_CGC_GATE 0x00c4
40 …EFC_SUVD_CGC_GATE 0x00c4
42 …ENT_SUVD_CGC_GATE 0x00c4
44 …IME_SUVD_CGC_GATE 0x00c4
46 …PPU_SUVD_CGC_GATE 0x00c4
[all …]
H A Dvcn_4_0_3_offset.h29 // base address: 0x1fb00
30 …UVD_TOP_CTRL 0x00c0
32 …UVD_CGC_GATE 0x00c1
34 …UVD_CGC_CTRL 0x00c2
36 …AVM_SUVD_CGC_GATE 0x00c4
38 …CDEFE_SUVD_CGC_GATE 0x00c4
40 …EFC_SUVD_CGC_GATE 0x00c4
42 …ENT_SUVD_CGC_GATE 0x00c4
44 …IME_SUVD_CGC_GATE 0x00c4
46 …PPU_SUVD_CGC_GATE 0x00c4
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/
H A Dgf100.fuc3.h3 /* 0x0000: ctx_object */
4 0x00000000,
5 /* 0x0004: ctx_query_address_high */
6 0x00000000,
7 /* 0x0008: ctx_query_address_low */
8 0x00000000,
9 /* 0x000c: ctx_query_counter */
10 0x00000000,
11 /* 0x0010: ctx_src_address_high */
12 0x00000000,
[all …]
/linux/sound/soc/codecs/
H A Drt1015.h17 #define RT1015_DEVICE_ID_VAL 0x1011
18 #define RT1015_DEVICE_ID_VAL2 0x1015
20 #define RT1015_RESET 0x0000
21 #define RT1015_CLK2 0x0004
22 #define RT1015_CLK3 0x0006
23 #define RT1015_PLL1 0x000a
24 #define RT1015_PLL2 0x000c
25 #define RT1015_DUM_RW1 0x000e
26 #define RT1015_DUM_RW2 0x0010
27 #define RT1015_DUM_RW3 0x0012
[all …]
H A Drt1011.h11 #define RT1011_DEVICE_ID_NUM 0x1011
13 #define RT1011_RESET 0x0000
14 #define RT1011_CLK_1 0x0002
15 #define RT1011_CLK_2 0x0004
16 #define RT1011_CLK_3 0x0006
17 #define RT1011_CLK_4 0x0008
18 #define RT1011_PLL_1 0x000a
19 #define RT1011_PLL_2 0x000c
20 #define RT1011_SRC_1 0x000e
21 #define RT1011_SRC_2 0x0010
[all …]
H A Drt1015.c39 { 0x0000, 0x0000 },
40 { 0x0004, 0xa000 },
41 { 0x0006, 0x0003 },
42 { 0x000a, 0x081e },
43 { 0x000c, 0x0006 },
44 { 0x000e, 0x0000 },
45 { 0x0010, 0x0000 },
46 { 0x0012, 0x0000 },
47 { 0x0014, 0x0000 },
48 { 0x0016, 0x0000 },
[all …]
H A Dwm5100-tables.c815 { 0x0000, 0x0000 }, /* R0 - software reset */
816 { 0x0001, 0x0000 }, /* R1 - Device Revision */
817 { 0x0010, 0x0801 }, /* R16 - Ctrl IF 1 */
818 { 0x0020, 0x0000 }, /* R32 - Tone Generator 1 */
819 { 0x0030, 0x0000 }, /* R48 - PWM Drive 1 */
820 { 0x0031, 0x0100 }, /* R49 - PWM Drive 2 */
821 { 0x0032, 0x0100 }, /* R50 - PWM Drive 3 */
822 { 0x0100, 0x0002 }, /* R256 - Clocking 1 */
823 { 0x0101, 0x0000 }, /* R257 - Clocking 3 */
824 { 0x0102, 0x0011 }, /* R258 - Clocking 4 */
[all …]
H A Drt1011.c37 { RT1011_POWER_9, 0xa840 },
39 { RT1011_ADC_SET_5, 0x0a20 },
40 { RT1011_DAC_SET_2, 0xa032 },
42 { RT1011_SPK_PRO_DC_DET_1, 0xb00c },
43 { RT1011_SPK_PRO_DC_DET_2, 0xcccc },
45 { RT1011_A_TIMING_1, 0x6054 },
47 { RT1011_POWER_7, 0x3e55 },
48 { RT1011_POWER_8, 0x0520 },
49 { RT1011_BOOST_CON_1, 0xe188 },
50 { RT1011_POWER_4, 0x16f2 },
[all …]
/linux/include/linux/bcma/
H A Dbcma.h62 #define BCMA_MANUF_ARM 0x43B
63 #define BCMA_MANUF_MIPS 0x4A7
64 #define BCMA_MANUF_BCM 0x4BF
67 #define BCMA_CL_SIM 0x0
68 #define BCMA_CL_EROM 0x1
69 #define BCMA_CL_CORESIGHT 0x9
70 #define BCMA_CL_VERIF 0xB
71 #define BCMA_CL_OPTIMO 0xD
72 #define BCMA_CL_GEN 0xE
73 #define BCMA_CL_PRIMECELL 0xF
[all …]
/linux/drivers/gpio/
H A Dgpio-f7188x.c23 #define SIO_LDSEL 0x07 /* Logical device select */
24 #define SIO_DEVID 0x20 /* Device ID (2 bytes) */
26 #define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
27 #define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
32 #define SIO_FINTEK_DEVREV 0x22 /* Fintek Device revision */
33 #define SIO_FINTEK_MANID 0x23 /* Fintek ID (2 bytes) */
35 #define SIO_FINTEK_ID 0x1934 /* Manufacturer ID */
37 #define SIO_F71869_ID 0x0814 /* F71869 chipset ID */
38 #define SIO_F71869A_ID 0x1007 /* F71869A chipset ID */
39 #define SIO_F71882_ID 0x0541 /* F71882 chipset ID */
[all …]
/linux/drivers/watchdog/
H A Df71808e_wdt.c21 #define SIO_F71808FG_LD_WDT 0x07 /* Watchdog timer logical device */
22 #define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
23 #define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
25 #define SIO_REG_LDSEL 0x07 /* Logical device select */
26 #define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
27 #define SIO_REG_DEVREV 0x22 /* Device revision */
28 #define SIO_REG_MANID 0x23 /* Fintek ID (2 bytes) */
29 #define SIO_REG_CLOCK_SEL 0x26 /* Clock select */
30 #define SIO_REG_ROM_ADDR_SEL 0x27 /* ROM address select */
31 #define SIO_F81866_REG_PORT_SEL 0x27 /* F81866 Multi-Function Register */
[all …]
/linux/drivers/net/wireless/realtek/rtl818x/rtl8187/
H A Drtl8225.c28 usb_control_msg(priv->udev, usb_rcvctrlpipe(priv->udev, 0), in rtl818x_ioread8_idx()
30 (unsigned long)addr, idx & 0x03, in rtl818x_ioread8_idx()
45 usb_control_msg(priv->udev, usb_rcvctrlpipe(priv->udev, 0), in rtl818x_ioread16_idx()
47 (unsigned long)addr, idx & 0x03, in rtl818x_ioread16_idx()
62 usb_control_msg(priv->udev, usb_rcvctrlpipe(priv->udev, 0), in rtl818x_ioread32_idx()
64 (unsigned long)addr, idx & 0x03, in rtl818x_ioread32_idx()
79 usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0), in rtl818x_iowrite8_idx()
81 (unsigned long)addr, idx & 0x03, in rtl818x_iowrite8_idx()
93 usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0), in rtl818x_iowrite16_idx()
95 (unsigned long)addr, idx & 0x03, in rtl818x_iowrite16_idx()
[all …]
/linux/drivers/media/platform/ti/vpe/
H A Dsc_coeff.h17 HS_UP_SCALE = 0,
31 0x001F, 0x1F90, 0x00D2, 0x06FE, 0x00D2, 0x1F90, 0x001F,
32 0x001C, 0x1F9E, 0x009F, 0x06FB, 0x0108, 0x1F82, 0x0022,
33 0x0019, 0x1FAC, 0x006F, 0x06F3, 0x0140, 0x1F74, 0x0025,
34 0x0016, 0x1FB9, 0x0041, 0x06E7, 0x017B, 0x1F66, 0x0028,
35 0x0013, 0x1FC6, 0x0017, 0x06D6, 0x01B7, 0x1F58, 0x002B,
36 0x0010, 0x1FD3, 0x1FEF, 0x06C0, 0x01F6, 0x1F4B, 0x002D,
37 0x000E, 0x1FDF, 0x1FCB, 0x06A5, 0x0235, 0x1F3F, 0x002F,
38 0x000B, 0x1FEA, 0x1FAA, 0x0686, 0x0277, 0x1F33, 0x0031,
39 0x0009, 0x1FF5, 0x1F8C, 0x0663, 0x02B8, 0x1F28, 0x0033,
[all …]
/linux/drivers/mfd/
H A Dwm8994-regmap.c18 { 0x0001, 0x0000 }, /* R1 - Power Management (1) */
19 { 0x0002, 0x6000 }, /* R2 - Power Management (2) */
20 { 0x0003, 0x0000 }, /* R3 - Power Management (3) */
21 { 0x0004, 0x0000 }, /* R4 - Power Management (4) */
22 { 0x0005, 0x0000 }, /* R5 - Power Management (5) */
23 { 0x0006, 0x0000 }, /* R6 - Power Management (6) */
24 { 0x0015, 0x0000 }, /* R21 - Input Mixer (1) */
25 { 0x0018, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
26 { 0x0019, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
27 { 0x001A, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/
H A Dgk208.fuc5.h3 /* 0x0000: proc_kern */
4 0x52544e49,
5 0x00000000,
6 0x00000000,
7 0x00000000,
8 0x00000000,
9 0x00000000,
10 0x00000000,
11 0x00000000,
12 0x00000000,
[all …]
/linux/drivers/net/wireless/realtek/rtl818x/rtl8180/
H A Drtl8225.c29 bangdata = (data << 4) | (addr & 0xf); in rtl8225_write()
31 reg80 = rtl818x_ioread16(priv, &priv->map->RFPinsOutput) & 0xfff3; in rtl8225_write()
34 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, reg82 | 0x7); in rtl8225_write()
37 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, reg84 | 0x7 | 0x400); in rtl8225_write()
48 for (i = 15; i >= 0; i--) { in rtl8225_write()
69 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, reg84 | 0x400); in rtl8225_write()
70 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF); in rtl8225_write()
81 reg84 = rtl818x_ioread16(priv, &priv->map->RFPinsSelect) | 0x400; in rtl8225_read()
83 reg80 &= ~0xF; in rtl8225_read()
85 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, reg82 | 0x000F); in rtl8225_read()
[all …]
/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c33 #define COMPHY_LANE2_INDIR_ADDR 0x0
34 #define COMPHY_LANE2_INDIR_DATA 0x4
37 #define COMPHY_LANE2_REGS_BASE 0x200
43 #define COMPHY_LANE_REG_DIRECT(reg) (((reg) & 0x7FF) << 1)
46 #define COMPHY_POWER_PLL_CTRL 0x01
55 #define REF_FREF_SEL_MASK GENMASK(4, 0)
56 #define REF_FREF_SEL_SERDES_25MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x1)
57 #define REF_FREF_SEL_SERDES_40MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x3)
58 #define REF_FREF_SEL_SERDES_50MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x4)
59 #define REF_FREF_SEL_PCIE_USB3_25MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x2)
[all …]
/linux/fs/smb/client/
H A Dwinucase.c23 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
24 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
25 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
26 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
27 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
28 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
29 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
30 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
31 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
32 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
[all …]
/linux/drivers/hwmon/
H A Df71882fg.c24 #define SIO_F71858FG_LD_HWM 0x02 /* Hardware monitor logical device */
25 #define SIO_F71882FG_LD_HWM 0x04 /* Hardware monitor logical device */
26 #define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
27 #define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
29 #define SIO_REG_LDSEL 0x07 /* Logical device select */
30 #define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
31 #define SIO_REG_DEVREV 0x22 /* Device revision */
32 #define SIO_REG_MANID 0x23 /* Fintek ID (2 bytes) */
33 #define SIO_REG_ENABLE 0x30 /* Logical device enable */
34 #define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsm8350.dtsi40 #clock-cells = <0>;
48 #clock-cells = <0>;
54 #size-cells = <0>;
56 cpu0: cpu@0 {
59 reg = <0x0 0x0>;
60 clocks = <&cpufreq_hw 0>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
83 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw 0>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_1_offset.h27 // base address: 0x0
28 …DENTIST_DISPCLK_CNTL 0x0064
33 // base address: 0x0
34 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
36 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
38 …PHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
40 …PHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
42 …DP_DTO_DBUF_EN 0x0044
44 …DSCCLK3_DTO_PARAM 0x0045
46 …DPREFCLK_CGTT_BLK_CTRL_REG 0x0048
[all …]
H A Ddcn_4_1_0_offset.h11 // base address: 0x0
12 …DENTIST_DISPCLK_CNTL 0x0064
17 // base address: 0x0
18 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
20 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
22 …PHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
24 …PHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
26 …DP_DTO_DBUF_EN 0x0044
28 …DSCCLK3_DTO_PARAM 0x0045
30 …DSCCLK4_DTO_PARAM 0x0046
[all …]
H A Ddcn_3_6_0_offset.h11 // base address: 0x1300000
12 …OBAL_CAPABILITIES 0x4b7000
14 …NOR_VERSION 0x4b7000
16 …JOR_VERSION 0x4b7000
18 …TPUT_PAYLOAD_CAPABILITY 0x4b7001
20 …PUT_PAYLOAD_CAPABILITY 0x4b7001
22 …OBAL_CONTROL 0x4b7002
24 …KE_ENABLE 0x4b7003
26 …ATE_CHANGE_STATUS 0x4b7003
28 …OBAL_STATUS 0x4b7004
[all …]

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