Lines Matching +full:0 +full:x0541
40 #clock-cells = <0>;
48 #clock-cells = <0>;
54 #size-cells = <0>;
56 cpu0: cpu@0 {
59 reg = <0x0 0x0>;
60 clocks = <&cpufreq_hw 0>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
83 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw 0>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
102 reg = <0x0 0x200>;
103 clocks = <&cpufreq_hw 0>;
106 qcom,freq-domain = <&cpufreq_hw 0>;
121 reg = <0x0 0x300>;
122 clocks = <&cpufreq_hw 0>;
125 qcom,freq-domain = <&cpufreq_hw 0>;
140 reg = <0x0 0x400>;
159 reg = <0x0 0x500>;
178 reg = <0x0 0x600>;
197 reg = <0x0 0x700>;
252 little_cpu_sleep_0: cpu-sleep-0-0 {
255 arm,psci-suspend-param = <0x40000004>;
262 big_cpu_sleep_0: cpu-sleep-1-0 {
265 arm,psci-suspend-param = <0x40000004>;
274 cluster_sleep_apss_off: cluster-sleep-0 {
276 arm,psci-suspend-param = <0x41000044>;
284 arm,psci-suspend-param = <0x4100c344>;
295 qcom,dload-mode = <&tcsr 0x13000>;
303 reg = <0x0 0x80000000 0x0 0x0>;
326 #power-domain-cells = <0>;
332 #power-domain-cells = <0>;
338 #power-domain-cells = <0>;
344 #power-domain-cells = <0>;
350 #power-domain-cells = <0>;
356 #power-domain-cells = <0>;
362 #power-domain-cells = <0>;
368 #power-domain-cells = <0>;
374 #power-domain-cells = <0>;
423 reg = <0x0 0x80000000 0x0 0x600000>;
429 reg = <0x0 0x80700000 0x0 0x160000>;
434 reg = <0x0 0x80860000 0x0 0x20000>;
439 reg = <0x0 0x80880000 0x0 0x14000>;
445 reg = <0x0 0x80900000 0x0 0x200000>;
451 reg = <0x0 0x80b00000 0x0 0x100000>;
456 reg = <0x0 0x80c00000 0x0 0x4600000>;
461 reg = <0x0 0x85200000 0x0 0x500000>;
466 reg = <0x0 0x85700000 0x0 0x500000>;
471 reg = <0x0 0x85c00000 0x0 0x500000>;
476 reg = <0x0 0x86100000 0x0 0x2100000>;
481 reg = <0x0 0x88200000 0x0 0x1500000>;
486 reg = <0x0 0x89700000 0x0 0x1e00000>;
491 reg = <0x0 0x8b500000 0x0 0x10000>;
496 reg = <0x0 0x8b510000 0x0 0xa000>;
501 reg = <0x0 0x8b51a000 0x0 0x2000>;
506 reg = <0x0 0x8b600000 0x0 0x100000>;
511 reg = <0x0 0x8b800000 0x0 0x10000000>;
517 reg = <0x0 0x9b800000 0x0 0x280000>;
525 reg = <0x0 0xd0000000 0x0 0x800000>;
530 reg = <0x0 0xd0800000 0x0 0x76f7000>;
535 reg = <0x0 0xd7ef7000 0x0 0x9000>;
540 reg = <0x0 0xd7f00000 0x0 0x80000>;
545 reg = <0x0 0xd7f80000 0x0 0x80000>;
550 reg = <0x0 0xd8800000 0x0 0x6800000>;
564 qcom,local-pid = <0>;
588 qcom,local-pid = <0>;
612 qcom,local-pid = <0>;
647 qcom,local-pid = <0>;
662 soc: soc@0 {
665 ranges = <0 0 0 0 0x10 0>;
666 dma-ranges = <0 0 0 0 0x10 0>;
671 reg = <0x0 0x00100000 0x0 0x1f0000>;
691 <0>,
692 <0>,
693 <0>,
694 <&ufs_mem_phy 0>,
698 <0>;
703 reg = <0 0x00408000 0 0x1000>;
712 reg = <0 0x00800000 0 0x60000>;
726 dma-channel-mask = <0xff>;
727 iommus = <&apps_smmu 0x5f6 0x0>;
734 reg = <0x0 0x008c0000 0x0 0x6000>;
738 iommus = <&apps_smmu 0x5e3 0x0>;
746 reg = <0 0x00880000 0 0x4000>;
750 pinctrl-0 = <&qup_i2c14_default>;
752 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
753 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
756 #size-cells = <0>;
762 reg = <0 0x00880000 0 0x4000>;
768 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
769 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
772 #size-cells = <0>;
778 reg = <0 0x00884000 0 0x4000>;
782 pinctrl-0 = <&qup_i2c15_default>;
784 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
788 #size-cells = <0>;
794 reg = <0 0x00884000 0 0x4000>;
800 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
804 #size-cells = <0>;
810 reg = <0 0x00888000 0 0x4000>;
814 pinctrl-0 = <&qup_i2c16_default>;
816 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
820 #size-cells = <0>;
826 reg = <0 0x00888000 0 0x4000>;
832 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
836 #size-cells = <0>;
842 reg = <0 0x0088c000 0 0x4000>;
846 pinctrl-0 = <&qup_i2c17_default>;
848 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
852 #size-cells = <0>;
858 reg = <0 0x0088c000 0 0x4000>;
864 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
868 #size-cells = <0>;
876 reg = <0 0x00890000 0 0x4000>;
882 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
886 #size-cells = <0>;
892 reg = <0 0x00890000 0 0x4000>;
896 pinctrl-0 = <&qup_uart18_default>;
905 reg = <0 0x00894000 0 0x4000>;
909 pinctrl-0 = <&qup_i2c19_default>;
911 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
915 #size-cells = <0>;
921 reg = <0 0x00894000 0 0x4000>;
927 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
931 #size-cells = <0>;
938 reg = <0 0x00900000 0 0x60000>;
952 dma-channel-mask = <0x7e>;
953 iommus = <&apps_smmu 0x5b6 0x0>;
960 reg = <0x0 0x009c0000 0x0 0x6000>;
964 iommus = <&apps_smmu 0x5a3 0>;
972 reg = <0 0x00980000 0 0x4000>;
976 pinctrl-0 = <&qup_i2c0_default>;
978 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
979 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
982 #size-cells = <0>;
988 reg = <0 0x00980000 0 0x4000>;
994 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
995 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
998 #size-cells = <0>;
1004 reg = <0 0x00984000 0 0x4000>;
1008 pinctrl-0 = <&qup_i2c1_default>;
1010 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1014 #size-cells = <0>;
1020 reg = <0 0x00984000 0 0x4000>;
1026 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1030 #size-cells = <0>;
1036 reg = <0 0x00988000 0 0x4000>;
1040 pinctrl-0 = <&qup_i2c2_default>;
1042 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1046 #size-cells = <0>;
1052 reg = <0 0x00988000 0 0x4000>;
1058 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1062 #size-cells = <0>;
1068 reg = <0 0x0098c000 0 0x4000>;
1072 pinctrl-0 = <&qup_uart3_default_state>;
1083 reg = <0 0x0098c000 0 0x4000>;
1089 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1093 #size-cells = <0>;
1099 reg = <0 0x00990000 0 0x4000>;
1103 pinctrl-0 = <&qup_i2c4_default>;
1105 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1109 #size-cells = <0>;
1115 reg = <0 0x00990000 0 0x4000>;
1121 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1125 #size-cells = <0>;
1131 reg = <0 0x00994000 0 0x4000>;
1135 pinctrl-0 = <&qup_i2c5_default>;
1137 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1141 #size-cells = <0>;
1147 reg = <0 0x00994000 0 0x4000>;
1153 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1157 #size-cells = <0>;
1163 reg = <0 0x00998000 0 0x4000>;
1167 pinctrl-0 = <&qup_i2c6_default>;
1169 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1173 #size-cells = <0>;
1179 reg = <0 0x00998000 0 0x4000>;
1185 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1189 #size-cells = <0>;
1195 reg = <0 0x00998000 0 0x4000>;
1199 pinctrl-0 = <&qup_uart6_default>;
1208 reg = <0 0x0099c000 0 0x4000>;
1212 pinctrl-0 = <&qup_i2c7_default>;
1214 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1218 #size-cells = <0>;
1224 reg = <0 0x0099c000 0 0x4000>;
1230 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1234 #size-cells = <0>;
1241 reg = <0 0x00a00000 0 0x60000>;
1255 dma-channel-mask = <0xff>;
1256 iommus = <&apps_smmu 0x56 0x0>;
1263 reg = <0x0 0x00ac0000 0x0 0x6000>;
1267 iommus = <&apps_smmu 0x43 0>;
1275 reg = <0 0x00a80000 0 0x4000>;
1279 pinctrl-0 = <&qup_i2c8_default>;
1281 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1282 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1285 #size-cells = <0>;
1291 reg = <0 0x00a80000 0 0x4000>;
1297 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1298 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1301 #size-cells = <0>;
1307 reg = <0 0x00a84000 0 0x4000>;
1311 pinctrl-0 = <&qup_i2c9_default>;
1313 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1317 #size-cells = <0>;
1323 reg = <0 0x00a84000 0 0x4000>;
1329 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1333 #size-cells = <0>;
1339 reg = <0 0x00a88000 0 0x4000>;
1343 pinctrl-0 = <&qup_i2c10_default>;
1345 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1349 #size-cells = <0>;
1355 reg = <0 0x00a88000 0 0x4000>;
1361 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1365 #size-cells = <0>;
1371 reg = <0 0x00a8c000 0 0x4000>;
1375 pinctrl-0 = <&qup_i2c11_default>;
1377 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1381 #size-cells = <0>;
1387 reg = <0 0x00a8c000 0 0x4000>;
1393 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1397 #size-cells = <0>;
1403 reg = <0 0x00a90000 0 0x4000>;
1407 pinctrl-0 = <&qup_i2c12_default>;
1409 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1413 #size-cells = <0>;
1419 reg = <0 0x00a90000 0 0x4000>;
1425 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1429 #size-cells = <0>;
1435 reg = <0 0x00a94000 0 0x4000>;
1439 pinctrl-0 = <&qup_i2c13_default>;
1441 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1445 #size-cells = <0>;
1451 reg = <0 0x00a94000 0 0x4000>;
1457 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1461 #size-cells = <0>;
1468 reg = <0 0x010d3000 0 0x1000>;
1475 reg = <0 0x01500000 0 0xa580>;
1482 reg = <0 0x01580000 0 0x1000>;
1489 reg = <0 0x01680000 0 0x1c200>;
1496 reg = <0 0x016e0000 0 0x1f180>;
1503 reg = <0 0x01700000 0 0x33000>;
1510 reg = <0 0x01740000 0 0x1f080>;
1517 reg = <0 0x01c00000 0 0x3000>,
1518 <0 0x60000000 0 0xf1d>,
1519 <0 0x60000f20 0 0xa8>,
1520 <0 0x60001000 0 0x1000>,
1521 <0 0x60100000 0 0x100000>;
1524 linux,pci-domain = <0>;
1525 bus-range = <0x00 0xff>;
1531 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1532 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1553 interrupt-map-mask = <0 0 0 0x7>;
1554 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1555 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1556 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1557 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1578 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1579 <0x100 &apps_smmu 0x1c01 0x1>;
1591 pcie@0 {
1593 reg = <0x0 0x0 0x0 0x0 0x0>;
1594 bus-range = <0x01 0xff>;
1604 reg = <0 0x01c06000 0 0x2000>;
1618 #clock-cells = <0>;
1621 #phy-cells = <0>;
1628 reg = <0 0x01c08000 0 0x3000>,
1629 <0 0x40000000 0 0xf1d>,
1630 <0 0x40000f20 0 0xa8>,
1631 <0 0x40001000 0 0x1000>,
1632 <0 0x40100000 0 0x100000>;
1636 bus-range = <0x00 0xff>;
1642 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1643 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1664 interrupt-map-mask = <0 0 0 0x7>;
1665 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1666 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1667 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1668 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1687 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1688 <0x100 &apps_smmu 0x1c81 0x1>;
1700 pcie@0 {
1702 reg = <0x0 0x0 0x0 0x0 0x0>;
1703 bus-range = <0x01 0xff>;
1713 reg = <0 0x01c0e000 0 0x2000>;
1727 #clock-cells = <0>;
1730 #phy-cells = <0>;
1738 reg = <0 0x01d84000 0 0x3000>;
1749 iommus = <&apps_smmu 0xe0 0x0>;
1777 <0 0>,
1778 <0 0>,
1780 <0 0>,
1781 <0 0>,
1782 <0 0>,
1783 <0 0>;
1789 reg = <0 0x01d87000 0 0x1000>;
1800 resets = <&ufs_mem_hc 0>;
1804 #phy-cells = <0>;
1811 reg = <0 0x01dc4000 0 0x24000>;
1814 qcom,ee = <0>;
1818 iommus = <&apps_smmu 0x594 0x0011>,
1819 <&apps_smmu 0x596 0x0011>;
1824 reg = <0 0x01dfa000 0 0x6000>;
1827 iommus = <&apps_smmu 0x594 0x0011>,
1828 <&apps_smmu 0x596 0x0011>;
1829 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
1836 iommus = <&apps_smmu 0x5c0 0x0>,
1837 <&apps_smmu 0x5c2 0x0>;
1838 reg = <0 0x01e40000 0 0x8000>,
1839 <0 0x01e50000 0 0x4b20>,
1840 <0 0x01e04000 0 0x23000>;
1847 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1857 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1858 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1864 qcom,smem-states = <&ipa_smp2p_out 0>,
1874 reg = <0x0 0x01f40000 0x0 0x40000>;
1880 reg = <0x0 0x1fc0000 0x0 0x30000>;
1885 reg = <0x0 0x03000000 0x0 0x10000>;
1888 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1906 qcom,smem-states = <&smp2p_adsp_out 0>;
1926 #size-cells = <0>;
1942 #size-cells = <0>;
1960 #size-cells = <0>;
1962 iommus = <&apps_smmu 0x1801 0x0>;
1964 dai@0 {
1985 #sound-dai-cells = <0>;
1996 #size-cells = <0>;
2001 iommus = <&apps_smmu 0x1803 0x0>;
2007 iommus = <&apps_smmu 0x1804 0x0>;
2013 iommus = <&apps_smmu 0x1805 0x0>;
2021 reg = <0 0x033c0000 0 0x20000>,
2022 <0 0x03550000 0 0x10000>;
2030 gpio-ranges = <&lpass_tlmm 0 0 15>;
2036 reg = <0 0x03d00000 0 0x40000>,
2037 <0 0x03d9e000 0 0x1000>,
2038 <0 0x03d61000 0 0x800>;
2045 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>;
2117 reg = <0 0x03d6a000 0 0x34000>,
2118 <0 0x03de0000 0 0x10000>,
2119 <0 0x0b290000 0 0x10000>;
2146 iommus = <&adreno_smmu 5 0x400>;
2162 reg = <0 0x03d90000 0 0x9000>;
2177 reg = <0 0x03da0000 0 0x20000>;
2214 reg = <0 0x03c40000 0 0xf080>;
2221 reg = <0x0 0x04080000 0x0 0x10000>;
2224 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2239 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2245 qcom,smem-states = <&smp2p_modem_out 0>;
2263 reg = <0 0x05c00000 0 0x4000>;
2266 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2284 qcom,smem-states = <&smp2p_slpi_out 0>;
2305 #size-cells = <0>;
2310 iommus = <&apps_smmu 0x0541 0x0>;
2316 iommus = <&apps_smmu 0x0542 0x0>;
2322 iommus = <&apps_smmu 0x0543 0x0>;
2331 reg = <0 0x08804000 0 0x1000>;
2342 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2343 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2345 iommus = <&apps_smmu 0x4a0 0x0>;
2371 reg = <0 0x088e3000 0 0x400>;
2373 #phy-cells = <0>;
2384 reg = <0 0x088e4000 0 0x400>;
2386 #phy-cells = <0>;
2397 reg = <0x0 0x088e7000 0x0 0x84>;
2402 reg = <0 0x088e8000 0 0x3000>;
2423 #size-cells = <0>;
2425 port@0 {
2426 reg = <0>;
2452 reg = <0 0x088eb000 0 0x2000>;
2464 #clock-cells = <0>;
2465 #phy-cells = <0>;
2475 reg = <0 0x090c0000 0 0x4200>;
2482 reg = <0 0x09100000 0 0xb4000>;
2489 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
2490 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
2491 <0 0x09600000 0 0x58000>;
2498 reg = <0 0x0a0c0000 0 0xa180>;
2505 reg = <0x0 0x0a300000 0x0 0x10000>;
2508 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2522 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
2528 qcom,smem-states = <&smp2p_cdsp_out 0>;
2549 #size-cells = <0>;
2554 iommus = <&apps_smmu 0x2161 0x0400>,
2555 <&apps_smmu 0x1181 0x0420>;
2561 iommus = <&apps_smmu 0x2162 0x0400>,
2562 <&apps_smmu 0x1182 0x0420>;
2568 iommus = <&apps_smmu 0x2163 0x0400>,
2569 <&apps_smmu 0x1183 0x0420>;
2575 iommus = <&apps_smmu 0x2164 0x0400>,
2576 <&apps_smmu 0x1184 0x0420>;
2582 iommus = <&apps_smmu 0x2165 0x0400>,
2583 <&apps_smmu 0x1185 0x0420>;
2589 iommus = <&apps_smmu 0x2166 0x0400>,
2590 <&apps_smmu 0x1186 0x0420>;
2596 iommus = <&apps_smmu 0x2167 0x0400>,
2597 <&apps_smmu 0x1187 0x0420>;
2603 iommus = <&apps_smmu 0x2168 0x0400>,
2604 <&apps_smmu 0x1188 0x0420>;
2614 reg = <0 0x0a6f8800 0 0x400>;
2650 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
2651 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
2656 reg = <0 0x0a600000 0 0xcd00>;
2658 iommus = <&apps_smmu 0x0 0x0>;
2669 #size-cells = <0>;
2671 port@0 {
2672 reg = <0>;
2691 reg = <0 0x0a8f8800 0 0x400>;
2729 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
2730 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
2735 reg = <0 0x0a800000 0 0xcd00>;
2737 iommus = <&apps_smmu 0x20 0x0>;
2750 reg = <0 0x0ae00000 0 0x1000>;
2753 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
2754 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>,
2774 iommus = <&apps_smmu 0x820 0x402>;
2784 reg = <0 0x0ae01000 0 0x8f000>,
2785 <0 0x0aeb0000 0 0x3000>;
2808 interrupts = <0>;
2841 #size-cells = <0>;
2843 port@0 {
2844 reg = <0>;
2868 reg = <0 0xae90000 0 0x200>,
2869 <0 0xae90200 0 0x200>,
2870 <0 0xae90400 0 0x600>,
2871 <0 0xae91000 0 0x400>,
2872 <0 0xae91400 0 0x400>;
2894 #sound-dai-cells = <0>;
2903 #size-cells = <0>;
2905 port@0 {
2906 reg = <0>;
2948 reg = <0 0x0ae94000 0 0x400>;
2979 #size-cells = <0>;
3009 #size-cells = <0>;
3011 port@0 {
3012 reg = <0>;
3028 reg = <0 0x0ae94400 0 0x200>,
3029 <0 0x0ae94600 0 0x280>,
3030 <0 0x0ae94900 0 0x27c>;
3036 #phy-cells = <0>;
3047 reg = <0 0x0ae96000 0 0x400>;
3078 #size-cells = <0>;
3108 #size-cells = <0>;
3110 port@0 {
3111 reg = <0>;
3127 reg = <0 0x0ae96400 0 0x200>,
3128 <0 0x0ae96600 0 0x280>,
3129 <0 0x0ae96900 0 0x27c>;
3135 #phy-cells = <0>;
3147 reg = <0 0x0af00000 0 0x10000>;
3171 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
3172 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
3183 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3184 <0 0x0c222000 0 0x8>; /* SROT */
3194 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3195 <0 0x0c223000 0 0x8>; /* SROT */
3205 reg = <0 0x0c300000 0 0x400>;
3210 #clock-cells = <0>;
3215 reg = <0 0x0c3f0000 0 0x400>;
3220 reg = <0x0 0x0c440000 0x0 0x1100>,
3221 <0x0 0x0c600000 0x0 0x2000000>,
3222 <0x0 0x0e600000 0x0 0x100000>,
3223 <0x0 0x0e700000 0x0 0xa0000>,
3224 <0x0 0x0c40a000 0x0 0x26000>;
3228 qcom,ee = <0>;
3229 qcom,channel = <0>;
3231 #size-cells = <0>;
3238 reg = <0 0x0f100000 0 0x300000>;
3244 gpio-ranges = <&tlmm 0 0 204>;
3441 reg = <0 0x15000000 0 0x100000>;
3550 redistributor-stride = <0 0x20000>;
3551 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3552 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3560 ranges = <0 0 0 0x20000000>;
3561 reg = <0x0 0x17c20000 0x0 0x1000>;
3565 frame-number = <0>;
3568 reg = <0x17c21000 0x1000>,
3569 <0x17c22000 0x1000>;
3575 reg = <0x17c23000 0x1000>;
3582 reg = <0x17c25000 0x1000>;
3589 reg = <0x17c27000 0x1000>;
3596 reg = <0x17c29000 0x1000>;
3603 reg = <0x17c2b000 0x1000>;
3610 reg = <0x17c2d000 0x1000>;
3618 reg = <0x0 0x18200000 0x0 0x10000>,
3619 <0x0 0x18210000 0x0 0x10000>,
3620 <0x0 0x18220000 0x0 0x10000>;
3621 reg-names = "drv-0", "drv-1", "drv-2";
3625 qcom,tcs-offset = <0xd00>;
3628 <WAKE_TCS 3>, <CONTROL_TCS 0>;
3695 reg = <0 0x18591000 0 0x1000>,
3696 <0 0x18592000 0 0x1000>,
3697 <0 0x18593000 0 0x1000>;
3703 interrupt-names = "dcvsh-irq-0",
4235 thermal-sensors = <&tsens0 0>;
4287 thermal-sensors = <&tsens1 0>;