H A D | clk-xlnx-clock-wizard.c | 240 u32 value, regh, edged, p5en, p5fedge, regval, regval1; in clk_wzrd_ver_dynamic_reconfig() local 440 u32 regh, edged, p5en, p5fedge, value2, m, regval, regval1, value; in clk_wzrd_dynamic_ver_all_nolock() local 583 u32 edged, div2, p5en, edge, prediv2, all, regl, regh, mult; clk_wzrd_recalc_rate_all_ver() local 986 u32 regl, regh, edge, regld, reghd, edged, div; clk_wzrd_register_output_clocks() local [all...] |