clk/xilinx/clk-xlnx-clock-wizard.c

240 	u32 value, regh, edged, p5en, p5fedge, regval, regval1;
248 	regh = (value / 4);
261 	regval = regh | regh << WZRD_CLKFBOUT_H_SHIFT;
440 	u32 regh, edged, p5en, p5fedge, value2, m, regval, regval1, value;
453 	regh = m / WZRD_DUTY_CYCLE;
464 	regval1 = regh | regh << WZRD_CLKFBOUT_H_SHIFT;
470 	regh = (value2 / WZRD_DUTY_CYCLE);
474 	regval1 = regh | regh << WZRD_CLKFBOUT_H_SHIFT;
478 	regh = value / WZRD_O_DIV;
495 	regval = regh | regh << WZRD_CLKFBOUT_H_SHIFT;
583 	u32 edged, div2, p5en, edge, prediv2, all, regl, regh, mult;
591 	regh = FIELD_GET(WZRD_CLKFBOUT_H_MASK, reg);
593 	mult = regl + regh + edge;
618 	regh = FIELD_GET(WZRD_CLKFBOUT_H_MASK, reg);
619 	all = regh + regl + edged;
635 	regh = FIELD_GET(WZRD_CLKFBOUT_H_MASK, reg);
636 	div = regl + regh + edged;
986 	u32 regl, regh, edge, regld, reghd, edged, div;
1020 		regh = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 1)) &
1022 		mult = regl + regh + edge;