1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Analog Devices AD4851 DAS driver
4 *
5 * Copyright 2024 Analog Devices Inc.
6 */
7
8 #include <linux/array_size.h>
9 #include <linux/bitfield.h>
10 #include <linux/bits.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/err.h>
14 #include <linux/minmax.h>
15 #include <linux/mod_devicetable.h>
16 #include <linux/module.h>
17 #include <linux/mutex.h>
18 #include <linux/pwm.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/spi/spi.h>
22 #include <linux/types.h>
23 #include <linux/unaligned.h>
24 #include <linux/units.h>
25
26 #include <linux/iio/backend.h>
27 #include <linux/iio/iio.h>
28
29 #define AD4851_REG_INTERFACE_CONFIG_A 0x00
30 #define AD4851_REG_INTERFACE_CONFIG_B 0x01
31 #define AD4851_REG_PRODUCT_ID_L 0x04
32 #define AD4851_REG_PRODUCT_ID_H 0x05
33 #define AD4851_REG_DEVICE_CTRL 0x25
34 #define AD4851_REG_PACKET 0x26
35 #define AD4851_REG_OVERSAMPLE 0x27
36
37 #define AD4851_REG_CH_CONFIG_BASE 0x2A
38 #define AD4851_REG_CHX_SOFTSPAN(ch) ((0x12 * (ch)) + AD4851_REG_CH_CONFIG_BASE)
39 #define AD4851_REG_CHX_OFFSET(ch) (AD4851_REG_CHX_SOFTSPAN(ch) + 0x01)
40 #define AD4851_REG_CHX_OFFSET_LSB(ch) AD4851_REG_CHX_OFFSET(ch)
41 #define AD4851_REG_CHX_OFFSET_MID(ch) (AD4851_REG_CHX_OFFSET_LSB(ch) + 0x01)
42 #define AD4851_REG_CHX_OFFSET_MSB(ch) (AD4851_REG_CHX_OFFSET_MID(ch) + 0x01)
43 #define AD4851_REG_CHX_GAIN(ch) (AD4851_REG_CHX_OFFSET(ch) + 0x03)
44 #define AD4851_REG_CHX_GAIN_LSB(ch) AD4851_REG_CHX_GAIN(ch)
45 #define AD4851_REG_CHX_GAIN_MSB(ch) (AD4851_REG_CHX_GAIN(ch) + 0x01)
46 #define AD4851_REG_CHX_PHASE(ch) (AD4851_REG_CHX_GAIN(ch) + 0x02)
47 #define AD4851_REG_CHX_PHASE_LSB(ch) AD4851_REG_CHX_PHASE(ch)
48 #define AD4851_REG_CHX_PHASE_MSB(ch) (AD4851_REG_CHX_PHASE_LSB(ch) + 0x01)
49
50 #define AD4851_REG_TESTPAT_0(c) (0x38 + (c) * 0x12)
51 #define AD4851_REG_TESTPAT_1(c) (0x39 + (c) * 0x12)
52 #define AD4851_REG_TESTPAT_2(c) (0x3A + (c) * 0x12)
53 #define AD4851_REG_TESTPAT_3(c) (0x3B + (c) * 0x12)
54
55 #define AD4851_SW_RESET (BIT(7) | BIT(0))
56 #define AD4851_SDO_ENABLE BIT(4)
57 #define AD4851_SINGLE_INSTRUCTION BIT(7)
58 #define AD4851_REFBUF BIT(2)
59 #define AD4851_REFSEL BIT(1)
60 #define AD4851_ECHO_CLOCK_MODE BIT(0)
61
62 #define AD4851_PACKET_FORMAT_0 0
63 #define AD4851_PACKET_FORMAT_1 1
64 #define AD4851_PACKET_FORMAT_MASK GENMASK(1, 0)
65
66 #define AD4851_OS_EN_MSK BIT(7)
67 #define AD4851_OS_RATIO_MSK GENMASK(3, 0)
68
69 #define AD4851_TEST_PAT BIT(2)
70
71 #define AD4858_PACKET_SIZE_20 0
72 #define AD4858_PACKET_SIZE_24 1
73 #define AD4858_PACKET_SIZE_32 2
74
75 #define AD4857_PACKET_SIZE_16 0
76 #define AD4857_PACKET_SIZE_24 1
77
78 #define AD4851_TESTPAT_0_DEFAULT 0x2A
79 #define AD4851_TESTPAT_1_DEFAULT 0x3C
80 #define AD4851_TESTPAT_2_DEFAULT 0xCE
81 #define AD4851_TESTPAT_3_DEFAULT(c) (0x0A + (0x10 * (c)))
82
83 #define AD4851_SOFTSPAN_0V_2V5 0
84 #define AD4851_SOFTSPAN_N2V5_2V5 1
85 #define AD4851_SOFTSPAN_0V_5V 2
86 #define AD4851_SOFTSPAN_N5V_5V 3
87 #define AD4851_SOFTSPAN_0V_6V25 4
88 #define AD4851_SOFTSPAN_N6V25_6V25 5
89 #define AD4851_SOFTSPAN_0V_10V 6
90 #define AD4851_SOFTSPAN_N10V_10V 7
91 #define AD4851_SOFTSPAN_0V_12V5 8
92 #define AD4851_SOFTSPAN_N12V5_12V5 9
93 #define AD4851_SOFTSPAN_0V_20V 10
94 #define AD4851_SOFTSPAN_N20V_20V 11
95 #define AD4851_SOFTSPAN_0V_25V 12
96 #define AD4851_SOFTSPAN_N25V_25V 13
97 #define AD4851_SOFTSPAN_0V_40V 14
98 #define AD4851_SOFTSPAN_N40V_40V 15
99
100 #define AD4851_MAX_LANES 8
101 #define AD4851_MAX_IODELAY 32
102
103 #define AD4851_T_CNVH_NS 40
104 #define AD4851_T_CNVH_NS_MARGIN 10
105
106 #define AD4841_MAX_SCALE_AVAIL 8
107
108 #define AD4851_MAX_CH_NR 8
109 #define AD4851_CH_START 0
110
111 struct ad4851_scale {
112 unsigned int scale_val;
113 u8 reg_val;
114 };
115
116 static const struct ad4851_scale ad4851_scale_table_unipolar[] = {
117 { 2500, 0x0 },
118 { 5000, 0x2 },
119 { 6250, 0x4 },
120 { 10000, 0x6 },
121 { 12500, 0x8 },
122 { 20000, 0xA },
123 { 25000, 0xC },
124 { 40000, 0xE },
125 };
126
127 static const struct ad4851_scale ad4851_scale_table_bipolar[] = {
128 { 5000, 0x1 },
129 { 10000, 0x3 },
130 { 12500, 0x5 },
131 { 20000, 0x7 },
132 { 25000, 0x9 },
133 { 40000, 0xB },
134 { 50000, 0xD },
135 { 80000, 0xF },
136 };
137
138 static const unsigned int ad4851_scale_avail_unipolar[] = {
139 2500,
140 5000,
141 6250,
142 10000,
143 12500,
144 20000,
145 25000,
146 40000,
147 };
148
149 static const unsigned int ad4851_scale_avail_bipolar[] = {
150 5000,
151 10000,
152 12500,
153 20000,
154 25000,
155 40000,
156 50000,
157 80000,
158 };
159
160 struct ad4851_chip_info {
161 const char *name;
162 unsigned int product_id;
163 int num_scales;
164 unsigned long max_sample_rate_hz;
165 unsigned int resolution;
166 unsigned int max_channels;
167 int (*parse_channels)(struct iio_dev *indio_dev);
168 };
169
170 enum {
171 AD4851_SCAN_TYPE_NORMAL,
172 AD4851_SCAN_TYPE_RESOLUTION_BOOST,
173 };
174
175 struct ad4851_state {
176 struct spi_device *spi;
177 struct pwm_device *cnv;
178 struct iio_backend *back;
179 /*
180 * Synchronize access to members the of driver state, and ensure
181 * atomicity of consecutive regmap operations.
182 */
183 struct mutex lock;
184 struct regmap *regmap;
185 const struct ad4851_chip_info *info;
186 struct gpio_desc *pd_gpio;
187 bool resolution_boost_enabled;
188 unsigned long cnv_trigger_rate_hz;
189 unsigned int osr;
190 bool vrefbuf_en;
191 bool vrefio_en;
192 bool bipolar_ch[AD4851_MAX_CH_NR];
193 unsigned int scales_unipolar[AD4841_MAX_SCALE_AVAIL][2];
194 unsigned int scales_bipolar[AD4841_MAX_SCALE_AVAIL][2];
195 };
196
ad4851_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)197 static int ad4851_reg_access(struct iio_dev *indio_dev,
198 unsigned int reg,
199 unsigned int writeval,
200 unsigned int *readval)
201 {
202 struct ad4851_state *st = iio_priv(indio_dev);
203
204 if (readval)
205 return regmap_read(st->regmap, reg, readval);
206
207 return regmap_write(st->regmap, reg, writeval);
208 }
209
ad4851_set_sampling_freq(struct ad4851_state * st,unsigned int freq)210 static int ad4851_set_sampling_freq(struct ad4851_state *st, unsigned int freq)
211 {
212 struct pwm_state cnv_state = {
213 .duty_cycle = AD4851_T_CNVH_NS + AD4851_T_CNVH_NS_MARGIN,
214 .enabled = true,
215 };
216 int ret;
217
218 freq = clamp(freq, 1, st->info->max_sample_rate_hz);
219
220 cnv_state.period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, freq);
221
222 ret = pwm_apply_might_sleep(st->cnv, &cnv_state);
223 if (ret)
224 return ret;
225
226 st->cnv_trigger_rate_hz = freq;
227
228 return 0;
229 }
230
231 static const int ad4851_oversampling_ratios[] = {
232 1, 2, 4, 8, 16, 32, 64, 128,
233 256, 512, 1024, 2048, 4096, 8192, 16384, 32768,
234 65536,
235 };
236
ad4851_osr_to_regval(unsigned int ratio)237 static int ad4851_osr_to_regval(unsigned int ratio)
238 {
239 int i;
240
241 for (i = 1; i < ARRAY_SIZE(ad4851_oversampling_ratios); i++)
242 if (ratio == ad4851_oversampling_ratios[i])
243 return i - 1;
244
245 return -EINVAL;
246 }
247
__ad4851_get_scale(struct iio_dev * indio_dev,int scale_tbl,unsigned int * val,unsigned int * val2)248 static int __ad4851_get_scale(struct iio_dev *indio_dev, int scale_tbl,
249 unsigned int *val, unsigned int *val2)
250 {
251 const struct iio_scan_type *scan_type;
252 unsigned int tmp;
253
254 scan_type = iio_get_current_scan_type(indio_dev, &indio_dev->channels[0]);
255 if (IS_ERR(scan_type))
256 return PTR_ERR(scan_type);
257
258 tmp = ((u64)scale_tbl * MICRO) >> scan_type->realbits;
259 *val = tmp / MICRO;
260 *val2 = tmp % MICRO;
261
262 return 0;
263 }
264
ad4851_scale_fill(struct iio_dev * indio_dev)265 static int ad4851_scale_fill(struct iio_dev *indio_dev)
266 {
267 struct ad4851_state *st = iio_priv(indio_dev);
268 unsigned int i, val1, val2;
269 int ret;
270
271 for (i = 0; i < ARRAY_SIZE(ad4851_scale_avail_unipolar); i++) {
272 ret = __ad4851_get_scale(indio_dev,
273 ad4851_scale_avail_unipolar[i],
274 &val1, &val2);
275 if (ret)
276 return ret;
277
278 st->scales_unipolar[i][0] = val1;
279 st->scales_unipolar[i][1] = val2;
280 }
281
282 for (i = 0; i < ARRAY_SIZE(ad4851_scale_avail_bipolar); i++) {
283 ret = __ad4851_get_scale(indio_dev,
284 ad4851_scale_avail_bipolar[i],
285 &val1, &val2);
286 if (ret)
287 return ret;
288
289 st->scales_bipolar[i][0] = val1;
290 st->scales_bipolar[i][1] = val2;
291 }
292
293 return 0;
294 }
295
ad4851_set_oversampling_ratio(struct iio_dev * indio_dev,unsigned int osr)296 static int ad4851_set_oversampling_ratio(struct iio_dev *indio_dev,
297 unsigned int osr)
298 {
299 struct ad4851_state *st = iio_priv(indio_dev);
300 int val, ret;
301
302 guard(mutex)(&st->lock);
303
304 if (osr == 1) {
305 ret = regmap_clear_bits(st->regmap, AD4851_REG_OVERSAMPLE,
306 AD4851_OS_EN_MSK);
307 if (ret)
308 return ret;
309 } else {
310 val = ad4851_osr_to_regval(osr);
311 if (val < 0)
312 return -EINVAL;
313
314 ret = regmap_update_bits(st->regmap, AD4851_REG_OVERSAMPLE,
315 AD4851_OS_EN_MSK |
316 AD4851_OS_RATIO_MSK,
317 FIELD_PREP(AD4851_OS_EN_MSK, 1) |
318 FIELD_PREP(AD4851_OS_RATIO_MSK, val));
319 if (ret)
320 return ret;
321 }
322
323 /* Channel is ignored by the backend being used here */
324 ret = iio_backend_oversampling_ratio_set(st->back, 0, osr);
325 if (ret)
326 return ret;
327
328 switch (st->info->resolution) {
329 case 20:
330 switch (osr) {
331 case 0:
332 return -EINVAL;
333 case 1:
334 val = 20;
335 break;
336 default:
337 val = 24;
338 break;
339 }
340 break;
341 case 16:
342 val = 16;
343 break;
344 default:
345 return -EINVAL;
346 }
347
348 ret = iio_backend_data_size_set(st->back, val);
349 if (ret)
350 return ret;
351
352 if (osr == 1 || st->info->resolution == 16) {
353 ret = regmap_clear_bits(st->regmap, AD4851_REG_PACKET,
354 AD4851_PACKET_FORMAT_MASK);
355 if (ret)
356 return ret;
357
358 st->resolution_boost_enabled = false;
359 } else {
360 ret = regmap_update_bits(st->regmap, AD4851_REG_PACKET,
361 AD4851_PACKET_FORMAT_MASK,
362 FIELD_PREP(AD4851_PACKET_FORMAT_MASK, 1));
363 if (ret)
364 return ret;
365
366 st->resolution_boost_enabled = true;
367 }
368
369 if (st->osr != osr) {
370 ret = ad4851_scale_fill(indio_dev);
371 if (ret)
372 return ret;
373
374 st->osr = osr;
375 }
376
377 return 0;
378 }
379
ad4851_get_oversampling_ratio(struct ad4851_state * st,unsigned int * val)380 static int ad4851_get_oversampling_ratio(struct ad4851_state *st, unsigned int *val)
381 {
382 unsigned int osr;
383 int ret;
384
385 guard(mutex)(&st->lock);
386
387 ret = regmap_read(st->regmap, AD4851_REG_OVERSAMPLE, &osr);
388 if (ret)
389 return ret;
390
391 if (!FIELD_GET(AD4851_OS_EN_MSK, osr))
392 *val = 1;
393 else
394 *val = ad4851_oversampling_ratios[FIELD_GET(AD4851_OS_RATIO_MSK, osr) + 1];
395
396 st->osr = *val;
397
398 return IIO_VAL_INT;
399 }
400
ad4851_pwm_disable(void * data)401 static void ad4851_pwm_disable(void *data)
402 {
403 pwm_disable(data);
404 }
405
ad4851_setup(struct ad4851_state * st)406 static int ad4851_setup(struct ad4851_state *st)
407 {
408 unsigned int product_id;
409 int ret;
410
411 if (st->pd_gpio) {
412 /* To initiate a global reset, bring the PD pin high twice */
413 gpiod_set_value(st->pd_gpio, 1);
414 fsleep(1);
415 gpiod_set_value(st->pd_gpio, 0);
416 fsleep(1);
417 gpiod_set_value(st->pd_gpio, 1);
418 fsleep(1);
419 gpiod_set_value(st->pd_gpio, 0);
420 fsleep(1000);
421 } else {
422 ret = regmap_set_bits(st->regmap, AD4851_REG_INTERFACE_CONFIG_A,
423 AD4851_SW_RESET);
424 if (ret)
425 return ret;
426 }
427
428 if (st->vrefbuf_en) {
429 ret = regmap_set_bits(st->regmap, AD4851_REG_DEVICE_CTRL,
430 AD4851_REFBUF);
431 if (ret)
432 return ret;
433 }
434
435 if (st->vrefio_en) {
436 ret = regmap_set_bits(st->regmap, AD4851_REG_DEVICE_CTRL,
437 AD4851_REFSEL);
438 if (ret)
439 return ret;
440 }
441
442 ret = regmap_write(st->regmap, AD4851_REG_INTERFACE_CONFIG_B,
443 AD4851_SINGLE_INSTRUCTION);
444 if (ret)
445 return ret;
446
447 if (!(st->spi->mode & SPI_3WIRE)) {
448 ret = regmap_write(st->regmap, AD4851_REG_INTERFACE_CONFIG_A,
449 AD4851_SDO_ENABLE);
450 if (ret)
451 return ret;
452 }
453
454 ret = regmap_read(st->regmap, AD4851_REG_PRODUCT_ID_L, &product_id);
455 if (ret)
456 return ret;
457
458 if (product_id != st->info->product_id)
459 dev_info(&st->spi->dev, "Unknown product ID: 0x%02X\n",
460 product_id);
461
462 ret = regmap_set_bits(st->regmap, AD4851_REG_DEVICE_CTRL,
463 AD4851_ECHO_CLOCK_MODE);
464 if (ret)
465 return ret;
466
467 return regmap_write(st->regmap, AD4851_REG_PACKET, 0);
468 }
469
470 /*
471 * Find the longest consecutive sequence of false values from field
472 * and return starting index.
473 */
ad4851_find_opt(const unsigned long * field,unsigned int start,unsigned int nbits,unsigned int * val)474 static int ad4851_find_opt(const unsigned long *field, unsigned int start,
475 unsigned int nbits, unsigned int *val)
476 {
477 unsigned int bit = start, end, start_cnt, cnt = 0;
478
479 for_each_clear_bitrange_from(bit, end, field, start + nbits) {
480 if (end - bit > cnt) {
481 cnt = end - bit;
482 start_cnt = bit - start;
483 }
484 }
485
486 if (!cnt)
487 return -ENOENT;
488
489 *val = start_cnt;
490
491 return cnt;
492 }
493
ad4851_calibrate(struct iio_dev * indio_dev)494 static int ad4851_calibrate(struct iio_dev *indio_dev)
495 {
496 struct ad4851_state *st = iio_priv(indio_dev);
497 unsigned int opt_delay, num_lanes, delay, i, s;
498 enum iio_backend_interface_type interface_type;
499 DECLARE_BITMAP(pn_status, AD4851_MAX_LANES * AD4851_MAX_IODELAY);
500 bool status;
501 int c, ret;
502
503 ret = iio_backend_interface_type_get(st->back, &interface_type);
504 if (ret)
505 return ret;
506
507 switch (interface_type) {
508 case IIO_BACKEND_INTERFACE_SERIAL_CMOS:
509 num_lanes = indio_dev->num_channels;
510 break;
511 case IIO_BACKEND_INTERFACE_SERIAL_LVDS:
512 num_lanes = 1;
513 break;
514 default:
515 return -EINVAL;
516 }
517
518 if (st->info->resolution == 16) {
519 ret = iio_backend_data_size_set(st->back, 24);
520 if (ret)
521 return ret;
522
523 ret = regmap_write(st->regmap, AD4851_REG_PACKET,
524 AD4851_TEST_PAT | AD4857_PACKET_SIZE_24);
525 if (ret)
526 return ret;
527 } else {
528 ret = iio_backend_data_size_set(st->back, 32);
529 if (ret)
530 return ret;
531
532 ret = regmap_write(st->regmap, AD4851_REG_PACKET,
533 AD4851_TEST_PAT | AD4858_PACKET_SIZE_32);
534 if (ret)
535 return ret;
536 }
537
538 for (i = 0; i < indio_dev->num_channels; i++) {
539 ret = regmap_write(st->regmap, AD4851_REG_TESTPAT_0(i),
540 AD4851_TESTPAT_0_DEFAULT);
541 if (ret)
542 return ret;
543
544 ret = regmap_write(st->regmap, AD4851_REG_TESTPAT_1(i),
545 AD4851_TESTPAT_1_DEFAULT);
546 if (ret)
547 return ret;
548
549 ret = regmap_write(st->regmap, AD4851_REG_TESTPAT_2(i),
550 AD4851_TESTPAT_2_DEFAULT);
551 if (ret)
552 return ret;
553
554 ret = regmap_write(st->regmap, AD4851_REG_TESTPAT_3(i),
555 AD4851_TESTPAT_3_DEFAULT(i));
556 if (ret)
557 return ret;
558
559 ret = iio_backend_chan_enable(st->back,
560 indio_dev->channels[i].channel);
561 if (ret)
562 return ret;
563 }
564
565 for (i = 0; i < num_lanes; i++) {
566 for (delay = 0; delay < AD4851_MAX_IODELAY; delay++) {
567 ret = iio_backend_iodelay_set(st->back, i, delay);
568 if (ret)
569 return ret;
570
571 ret = iio_backend_chan_status(st->back, i, &status);
572 if (ret)
573 return ret;
574
575 __assign_bit(i * AD4851_MAX_IODELAY + delay, pn_status,
576 status);
577 }
578 }
579
580 for (i = 0; i < num_lanes; i++) {
581 c = ad4851_find_opt(pn_status, i * AD4851_MAX_IODELAY,
582 AD4851_MAX_IODELAY, &s);
583 if (c < 0)
584 return c;
585
586 opt_delay = s + c / 2;
587 ret = iio_backend_iodelay_set(st->back, i, opt_delay);
588 if (ret)
589 return ret;
590 }
591
592 for (i = 0; i < indio_dev->num_channels; i++) {
593 ret = iio_backend_chan_disable(st->back, i);
594 if (ret)
595 return ret;
596 }
597
598 ret = iio_backend_data_size_set(st->back, 20);
599 if (ret)
600 return ret;
601
602 return regmap_write(st->regmap, AD4851_REG_PACKET, 0);
603 }
604
ad4851_get_calibscale(struct ad4851_state * st,int ch,int * val,int * val2)605 static int ad4851_get_calibscale(struct ad4851_state *st, int ch, int *val, int *val2)
606 {
607 unsigned int reg_val;
608 int gain;
609 int ret;
610
611 guard(mutex)(&st->lock);
612
613 ret = regmap_read(st->regmap, AD4851_REG_CHX_GAIN_MSB(ch), ®_val);
614 if (ret)
615 return ret;
616
617 gain = reg_val << 8;
618
619 ret = regmap_read(st->regmap, AD4851_REG_CHX_GAIN_LSB(ch), ®_val);
620 if (ret)
621 return ret;
622
623 gain |= reg_val;
624
625 *val = gain;
626 *val2 = 15;
627
628 return IIO_VAL_FRACTIONAL_LOG2;
629 }
630
ad4851_set_calibscale(struct ad4851_state * st,int ch,int val,int val2)631 static int ad4851_set_calibscale(struct ad4851_state *st, int ch, int val,
632 int val2)
633 {
634 u64 gain;
635 u8 buf[2];
636 int ret;
637
638 if (val < 0 || val2 < 0)
639 return -EINVAL;
640
641 gain = val * MICRO + val2;
642 gain = DIV_U64_ROUND_CLOSEST(gain * 32768, MICRO);
643
644 put_unaligned_be16(gain, buf);
645
646 guard(mutex)(&st->lock);
647
648 ret = regmap_write(st->regmap, AD4851_REG_CHX_GAIN_MSB(ch), buf[0]);
649 if (ret)
650 return ret;
651
652 return regmap_write(st->regmap, AD4851_REG_CHX_GAIN_LSB(ch), buf[1]);
653 }
654
ad4851_get_calibbias(struct ad4851_state * st,int ch,int * val)655 static int ad4851_get_calibbias(struct ad4851_state *st, int ch, int *val)
656 {
657 unsigned int lsb, mid, msb;
658 int ret;
659
660 guard(mutex)(&st->lock);
661 /*
662 * After testing, the bulk_write operations doesn't work as expected
663 * here since the cs needs to be raised after each byte transaction.
664 */
665 ret = regmap_read(st->regmap, AD4851_REG_CHX_OFFSET_MSB(ch), &msb);
666 if (ret)
667 return ret;
668
669 ret = regmap_read(st->regmap, AD4851_REG_CHX_OFFSET_MID(ch), &mid);
670 if (ret)
671 return ret;
672
673 ret = regmap_read(st->regmap, AD4851_REG_CHX_OFFSET_LSB(ch), &lsb);
674 if (ret)
675 return ret;
676
677 if (st->info->resolution == 16) {
678 *val = msb << 8;
679 *val |= mid;
680 *val = sign_extend32(*val, 15);
681 } else {
682 *val = msb << 12;
683 *val |= mid << 4;
684 *val |= lsb >> 4;
685 *val = sign_extend32(*val, 19);
686 }
687
688 return IIO_VAL_INT;
689 }
690
ad4851_set_calibbias(struct ad4851_state * st,int ch,int val)691 static int ad4851_set_calibbias(struct ad4851_state *st, int ch, int val)
692 {
693 u8 buf[3];
694 int ret;
695
696 if (val < 0)
697 return -EINVAL;
698
699 if (st->info->resolution == 16)
700 put_unaligned_be16(val, buf);
701 else
702 put_unaligned_be24(val << 4, buf);
703
704 guard(mutex)(&st->lock);
705 /*
706 * After testing, the bulk_write operations doesn't work as expected
707 * here since the cs needs to be raised after each byte transaction.
708 */
709 ret = regmap_write(st->regmap, AD4851_REG_CHX_OFFSET_LSB(ch), buf[2]);
710 if (ret)
711 return ret;
712
713 ret = regmap_write(st->regmap, AD4851_REG_CHX_OFFSET_MID(ch), buf[1]);
714 if (ret)
715 return ret;
716
717 return regmap_write(st->regmap, AD4851_REG_CHX_OFFSET_MSB(ch), buf[0]);
718 }
719
ad4851_set_scale(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int val,int val2)720 static int ad4851_set_scale(struct iio_dev *indio_dev,
721 const struct iio_chan_spec *chan, int val, int val2)
722 {
723 struct ad4851_state *st = iio_priv(indio_dev);
724 unsigned int scale_val[2];
725 unsigned int i;
726 const struct ad4851_scale *scale_table;
727 size_t table_size;
728 int ret;
729
730 if (st->bipolar_ch[chan->channel]) {
731 scale_table = ad4851_scale_table_bipolar;
732 table_size = ARRAY_SIZE(ad4851_scale_table_bipolar);
733 } else {
734 scale_table = ad4851_scale_table_unipolar;
735 table_size = ARRAY_SIZE(ad4851_scale_table_unipolar);
736 }
737
738 for (i = 0; i < table_size; i++) {
739 ret = __ad4851_get_scale(indio_dev, scale_table[i].scale_val,
740 &scale_val[0], &scale_val[1]);
741 if (ret)
742 return ret;
743
744 if (scale_val[0] != val || scale_val[1] != val2)
745 continue;
746
747 return regmap_write(st->regmap,
748 AD4851_REG_CHX_SOFTSPAN(chan->channel),
749 scale_table[i].reg_val);
750 }
751
752 return -EINVAL;
753 }
754
ad4851_get_scale(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2)755 static int ad4851_get_scale(struct iio_dev *indio_dev,
756 const struct iio_chan_spec *chan, int *val,
757 int *val2)
758 {
759 struct ad4851_state *st = iio_priv(indio_dev);
760 const struct ad4851_scale *scale_table;
761 size_t table_size;
762 u32 softspan_val;
763 int i, ret;
764
765 if (st->bipolar_ch[chan->channel]) {
766 scale_table = ad4851_scale_table_bipolar;
767 table_size = ARRAY_SIZE(ad4851_scale_table_bipolar);
768 } else {
769 scale_table = ad4851_scale_table_unipolar;
770 table_size = ARRAY_SIZE(ad4851_scale_table_unipolar);
771 }
772
773 ret = regmap_read(st->regmap, AD4851_REG_CHX_SOFTSPAN(chan->channel),
774 &softspan_val);
775 if (ret)
776 return ret;
777
778 for (i = 0; i < table_size; i++) {
779 if (softspan_val == scale_table[i].reg_val)
780 break;
781 }
782
783 if (i == table_size)
784 return -EIO;
785
786 ret = __ad4851_get_scale(indio_dev, scale_table[i].scale_val, val,
787 val2);
788 if (ret)
789 return ret;
790
791 return IIO_VAL_INT_PLUS_MICRO;
792 }
793
ad4851_read_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long info)794 static int ad4851_read_raw(struct iio_dev *indio_dev,
795 const struct iio_chan_spec *chan,
796 int *val, int *val2, long info)
797 {
798 struct ad4851_state *st = iio_priv(indio_dev);
799
800 switch (info) {
801 case IIO_CHAN_INFO_SAMP_FREQ:
802 *val = st->cnv_trigger_rate_hz;
803 *val2 = st->osr;
804 return IIO_VAL_FRACTIONAL;
805 case IIO_CHAN_INFO_CALIBSCALE:
806 return ad4851_get_calibscale(st, chan->channel, val, val2);
807 case IIO_CHAN_INFO_SCALE:
808 return ad4851_get_scale(indio_dev, chan, val, val2);
809 case IIO_CHAN_INFO_CALIBBIAS:
810 return ad4851_get_calibbias(st, chan->channel, val);
811 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
812 return ad4851_get_oversampling_ratio(st, val);
813 default:
814 return -EINVAL;
815 }
816 }
817
ad4851_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)818 static int ad4851_write_raw(struct iio_dev *indio_dev,
819 struct iio_chan_spec const *chan,
820 int val, int val2, long info)
821 {
822 struct ad4851_state *st = iio_priv(indio_dev);
823
824 switch (info) {
825 case IIO_CHAN_INFO_SAMP_FREQ:
826 if (val < 0 || val2 < 0)
827 return -EINVAL;
828 return ad4851_set_sampling_freq(st, val * st->osr + val2 * st->osr / MICRO);
829 case IIO_CHAN_INFO_SCALE:
830 return ad4851_set_scale(indio_dev, chan, val, val2);
831 case IIO_CHAN_INFO_CALIBSCALE:
832 return ad4851_set_calibscale(st, chan->channel, val, val2);
833 case IIO_CHAN_INFO_CALIBBIAS:
834 return ad4851_set_calibbias(st, chan->channel, val);
835 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
836 return ad4851_set_oversampling_ratio(indio_dev, val);
837 default:
838 return -EINVAL;
839 }
840 }
841
ad4851_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)842 static int ad4851_update_scan_mode(struct iio_dev *indio_dev,
843 const unsigned long *scan_mask)
844 {
845 struct ad4851_state *st = iio_priv(indio_dev);
846 unsigned int c;
847 int ret;
848
849 for (c = 0; c < indio_dev->num_channels; c++) {
850 if (test_bit(c, scan_mask))
851 ret = iio_backend_chan_enable(st->back, c);
852 else
853 ret = iio_backend_chan_disable(st->back, c);
854 if (ret)
855 return ret;
856 }
857
858 return 0;
859 }
860
ad4851_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)861 static int ad4851_read_avail(struct iio_dev *indio_dev,
862 struct iio_chan_spec const *chan,
863 const int **vals, int *type, int *length,
864 long mask)
865 {
866 struct ad4851_state *st = iio_priv(indio_dev);
867
868 switch (mask) {
869 case IIO_CHAN_INFO_SCALE:
870 if (st->bipolar_ch[chan->channel]) {
871 *vals = (const int *)st->scales_bipolar;
872 *type = IIO_VAL_INT_PLUS_MICRO;
873 /* Values are stored in a 2D matrix */
874 *length = ARRAY_SIZE(ad4851_scale_avail_bipolar) * 2;
875 } else {
876 *vals = (const int *)st->scales_unipolar;
877 *type = IIO_VAL_INT_PLUS_MICRO;
878 /* Values are stored in a 2D matrix */
879 *length = ARRAY_SIZE(ad4851_scale_avail_unipolar) * 2;
880 }
881 return IIO_AVAIL_LIST;
882 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
883 *vals = ad4851_oversampling_ratios;
884 *length = ARRAY_SIZE(ad4851_oversampling_ratios);
885 *type = IIO_VAL_INT;
886 return IIO_AVAIL_LIST;
887 default:
888 return -EINVAL;
889 }
890 }
891
892 static const struct iio_scan_type ad4851_scan_type_20_u[] = {
893 [AD4851_SCAN_TYPE_NORMAL] = {
894 .sign = 'u',
895 .realbits = 20,
896 .storagebits = 32,
897 },
898 [AD4851_SCAN_TYPE_RESOLUTION_BOOST] = {
899 .sign = 'u',
900 .realbits = 24,
901 .storagebits = 32,
902 },
903 };
904
905 static const struct iio_scan_type ad4851_scan_type_20_b[] = {
906 [AD4851_SCAN_TYPE_NORMAL] = {
907 .sign = 's',
908 .realbits = 20,
909 .storagebits = 32,
910 },
911 [AD4851_SCAN_TYPE_RESOLUTION_BOOST] = {
912 .sign = 's',
913 .realbits = 24,
914 .storagebits = 32,
915 },
916 };
917
ad4851_get_current_scan_type(const struct iio_dev * indio_dev,const struct iio_chan_spec * chan)918 static int ad4851_get_current_scan_type(const struct iio_dev *indio_dev,
919 const struct iio_chan_spec *chan)
920 {
921 struct ad4851_state *st = iio_priv(indio_dev);
922
923 return st->resolution_boost_enabled ? AD4851_SCAN_TYPE_RESOLUTION_BOOST
924 : AD4851_SCAN_TYPE_NORMAL;
925 }
926
927 #define AD4851_IIO_CHANNEL \
928 .type = IIO_VOLTAGE, \
929 .info_mask_separate = BIT(IIO_CHAN_INFO_CALIBSCALE) | \
930 BIT(IIO_CHAN_INFO_CALIBBIAS) | \
931 BIT(IIO_CHAN_INFO_SCALE), \
932 .info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE), \
933 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
934 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
935 .info_mask_shared_by_all_available = \
936 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
937 .indexed = 1
938
939 /*
940 * In case of AD4858_IIO_CHANNEL the scan_type is handled dynamically during the
941 * parse_channels function.
942 */
943 #define AD4858_IIO_CHANNEL \
944 { \
945 AD4851_IIO_CHANNEL \
946 }
947
948 #define AD4857_IIO_CHANNEL \
949 { \
950 AD4851_IIO_CHANNEL, \
951 .scan_type = { \
952 .sign = 'u', \
953 .realbits = 16, \
954 .storagebits = 16, \
955 }, \
956 }
957
ad4851_parse_channels_common(struct iio_dev * indio_dev,struct iio_chan_spec ** chans,const struct iio_chan_spec ad4851_chan)958 static int ad4851_parse_channels_common(struct iio_dev *indio_dev,
959 struct iio_chan_spec **chans,
960 const struct iio_chan_spec ad4851_chan)
961 {
962 struct ad4851_state *st = iio_priv(indio_dev);
963 struct device *dev = &st->spi->dev;
964 struct iio_chan_spec *channels, *chan_start;
965 unsigned int num_channels, reg;
966 unsigned int index = 0;
967 int ret;
968
969 num_channels = device_get_child_node_count(dev);
970 if (num_channels > AD4851_MAX_CH_NR)
971 return dev_err_probe(dev, -EINVAL, "Too many channels: %u\n",
972 num_channels);
973
974 channels = devm_kcalloc(dev, num_channels, sizeof(*channels), GFP_KERNEL);
975 if (!channels)
976 return -ENOMEM;
977
978 chan_start = channels;
979
980 device_for_each_child_node_scoped(dev, child) {
981 ret = fwnode_property_read_u32(child, "reg", ®);
982 if (ret)
983 return dev_err_probe(dev, ret,
984 "Missing channel number\n");
985 if (reg >= AD4851_MAX_CH_NR)
986 return dev_err_probe(dev, -EINVAL,
987 "Invalid channel number\n");
988 *channels = ad4851_chan;
989 channels->scan_index = index++;
990 channels->channel = reg;
991
992 if (fwnode_property_present(child, "diff-channels")) {
993 channels->channel2 = reg + st->info->max_channels;
994 channels->differential = 1;
995 }
996
997 st->bipolar_ch[reg] = fwnode_property_read_bool(child, "bipolar");
998
999 if (st->bipolar_ch[reg]) {
1000 channels->scan_type.sign = 's';
1001 } else {
1002 ret = regmap_write(st->regmap, AD4851_REG_CHX_SOFTSPAN(reg),
1003 AD4851_SOFTSPAN_0V_40V);
1004 if (ret)
1005 return ret;
1006 }
1007
1008 channels++;
1009 }
1010
1011 *chans = chan_start;
1012
1013 return num_channels;
1014 }
1015
ad4857_parse_channels(struct iio_dev * indio_dev)1016 static int ad4857_parse_channels(struct iio_dev *indio_dev)
1017 {
1018 struct iio_chan_spec *ad4851_channels;
1019 const struct iio_chan_spec ad4851_chan = AD4857_IIO_CHANNEL;
1020 int ret;
1021
1022 ret = ad4851_parse_channels_common(indio_dev, &ad4851_channels,
1023 ad4851_chan);
1024 if (ret < 0)
1025 return ret;
1026
1027 indio_dev->channels = ad4851_channels;
1028 indio_dev->num_channels = ret;
1029
1030 return 0;
1031 }
1032
ad4858_parse_channels(struct iio_dev * indio_dev)1033 static int ad4858_parse_channels(struct iio_dev *indio_dev)
1034 {
1035 struct ad4851_state *st = iio_priv(indio_dev);
1036 struct device *dev = &st->spi->dev;
1037 struct iio_chan_spec *ad4851_channels;
1038 const struct iio_chan_spec ad4851_chan = AD4858_IIO_CHANNEL;
1039 int ret, i = 0;
1040
1041 ret = ad4851_parse_channels_common(indio_dev, &ad4851_channels,
1042 ad4851_chan);
1043 if (ret < 0)
1044 return ret;
1045
1046 device_for_each_child_node_scoped(dev, child) {
1047 ad4851_channels[i].has_ext_scan_type = 1;
1048 if (fwnode_property_read_bool(child, "bipolar")) {
1049 ad4851_channels[i].ext_scan_type = ad4851_scan_type_20_b;
1050 ad4851_channels[i].num_ext_scan_type = ARRAY_SIZE(ad4851_scan_type_20_b);
1051 } else {
1052 ad4851_channels[i].ext_scan_type = ad4851_scan_type_20_u;
1053 ad4851_channels[i].num_ext_scan_type = ARRAY_SIZE(ad4851_scan_type_20_u);
1054 }
1055 i++;
1056 }
1057
1058 indio_dev->channels = ad4851_channels;
1059 indio_dev->num_channels = ret;
1060
1061 return 0;
1062 }
1063
1064 /*
1065 * parse_channels() function handles the rest of the channel related attributes
1066 * that are usually are stored in the chip info structure.
1067 */
1068 static const struct ad4851_chip_info ad4851_info = {
1069 .name = "ad4851",
1070 .product_id = 0x67,
1071 .max_sample_rate_hz = 250 * KILO,
1072 .resolution = 16,
1073 .max_channels = AD4851_MAX_CH_NR,
1074 .parse_channels = ad4857_parse_channels,
1075 };
1076
1077 static const struct ad4851_chip_info ad4852_info = {
1078 .name = "ad4852",
1079 .product_id = 0x66,
1080 .max_sample_rate_hz = 250 * KILO,
1081 .resolution = 20,
1082 .max_channels = AD4851_MAX_CH_NR,
1083 .parse_channels = ad4858_parse_channels,
1084 };
1085
1086 static const struct ad4851_chip_info ad4853_info = {
1087 .name = "ad4853",
1088 .product_id = 0x65,
1089 .max_sample_rate_hz = 1 * MEGA,
1090 .resolution = 16,
1091 .max_channels = AD4851_MAX_CH_NR,
1092 .parse_channels = ad4857_parse_channels,
1093 };
1094
1095 static const struct ad4851_chip_info ad4854_info = {
1096 .name = "ad4854",
1097 .product_id = 0x64,
1098 .max_sample_rate_hz = 1 * MEGA,
1099 .resolution = 20,
1100 .max_channels = AD4851_MAX_CH_NR,
1101 .parse_channels = ad4858_parse_channels,
1102 };
1103
1104 static const struct ad4851_chip_info ad4855_info = {
1105 .name = "ad4855",
1106 .product_id = 0x63,
1107 .max_sample_rate_hz = 250 * KILO,
1108 .resolution = 16,
1109 .max_channels = AD4851_MAX_CH_NR,
1110 .parse_channels = ad4857_parse_channels,
1111 };
1112
1113 static const struct ad4851_chip_info ad4856_info = {
1114 .name = "ad4856",
1115 .product_id = 0x62,
1116 .max_sample_rate_hz = 250 * KILO,
1117 .resolution = 20,
1118 .max_channels = AD4851_MAX_CH_NR,
1119 .parse_channels = ad4858_parse_channels,
1120 };
1121
1122 static const struct ad4851_chip_info ad4857_info = {
1123 .name = "ad4857",
1124 .product_id = 0x61,
1125 .max_sample_rate_hz = 1 * MEGA,
1126 .resolution = 16,
1127 .max_channels = AD4851_MAX_CH_NR,
1128 .parse_channels = ad4857_parse_channels,
1129 };
1130
1131 static const struct ad4851_chip_info ad4858_info = {
1132 .name = "ad4858",
1133 .product_id = 0x60,
1134 .max_sample_rate_hz = 1 * MEGA,
1135 .resolution = 20,
1136 .max_channels = AD4851_MAX_CH_NR,
1137 .parse_channels = ad4858_parse_channels,
1138 };
1139
1140 static const struct ad4851_chip_info ad4858i_info = {
1141 .name = "ad4858i",
1142 .product_id = 0x6F,
1143 .max_sample_rate_hz = 1 * MEGA,
1144 .resolution = 20,
1145 .max_channels = AD4851_MAX_CH_NR,
1146 .parse_channels = ad4858_parse_channels,
1147 };
1148
1149 static const struct iio_info ad4851_iio_info = {
1150 .debugfs_reg_access = ad4851_reg_access,
1151 .read_raw = ad4851_read_raw,
1152 .write_raw = ad4851_write_raw,
1153 .update_scan_mode = ad4851_update_scan_mode,
1154 .get_current_scan_type = ad4851_get_current_scan_type,
1155 .read_avail = ad4851_read_avail,
1156 };
1157
1158 static const struct regmap_config regmap_config = {
1159 .reg_bits = 16,
1160 .val_bits = 8,
1161 .read_flag_mask = BIT(7),
1162 };
1163
1164 static const char * const ad4851_power_supplies[] = {
1165 "vcc", "vdd", "vee", "vio",
1166 };
1167
ad4851_probe(struct spi_device * spi)1168 static int ad4851_probe(struct spi_device *spi)
1169 {
1170 struct iio_dev *indio_dev;
1171 struct device *dev = &spi->dev;
1172 struct ad4851_state *st;
1173 int ret;
1174
1175 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1176 if (!indio_dev)
1177 return -ENOMEM;
1178
1179 st = iio_priv(indio_dev);
1180 st->spi = spi;
1181
1182 ret = devm_mutex_init(dev, &st->lock);
1183 if (ret)
1184 return ret;
1185
1186 ret = devm_regulator_bulk_get_enable(dev,
1187 ARRAY_SIZE(ad4851_power_supplies),
1188 ad4851_power_supplies);
1189 if (ret)
1190 return dev_err_probe(dev, ret,
1191 "failed to get and enable supplies\n");
1192
1193 ret = devm_regulator_get_enable_optional(dev, "vddh");
1194 if (ret < 0 && ret != -ENODEV)
1195 return dev_err_probe(dev, ret, "failed to enable vddh voltage\n");
1196
1197 ret = devm_regulator_get_enable_optional(dev, "vddl");
1198 if (ret < 0 && ret != -ENODEV)
1199 return dev_err_probe(dev, ret, "failed to enable vddl voltage\n");
1200
1201 ret = devm_regulator_get_enable_optional(dev, "vrefbuf");
1202 if (ret < 0 && ret != -ENODEV)
1203 return dev_err_probe(dev, ret, "failed to enable vrefbuf voltage\n");
1204
1205 st->vrefbuf_en = ret != -ENODEV;
1206
1207 ret = devm_regulator_get_enable_optional(dev, "vrefio");
1208 if (ret < 0 && ret != -ENODEV)
1209 return dev_err_probe(dev, ret, "failed to enable vrefio voltage\n");
1210
1211 st->vrefio_en = ret != -ENODEV;
1212
1213 st->pd_gpio = devm_gpiod_get_optional(dev, "pd", GPIOD_OUT_LOW);
1214 if (IS_ERR(st->pd_gpio))
1215 return dev_err_probe(dev, PTR_ERR(st->pd_gpio),
1216 "Error on requesting pd GPIO\n");
1217
1218 st->cnv = devm_pwm_get(dev, NULL);
1219 if (IS_ERR(st->cnv))
1220 return dev_err_probe(dev, PTR_ERR(st->cnv),
1221 "Error on requesting pwm\n");
1222
1223 st->info = spi_get_device_match_data(spi);
1224 if (!st->info)
1225 return -ENODEV;
1226
1227 st->regmap = devm_regmap_init_spi(spi, ®map_config);
1228 if (IS_ERR(st->regmap))
1229 return PTR_ERR(st->regmap);
1230
1231 ret = ad4851_set_sampling_freq(st, HZ_PER_MHZ);
1232 if (ret)
1233 return ret;
1234
1235 ret = devm_add_action_or_reset(&st->spi->dev, ad4851_pwm_disable,
1236 st->cnv);
1237 if (ret)
1238 return ret;
1239
1240 ret = ad4851_setup(st);
1241 if (ret)
1242 return ret;
1243
1244 indio_dev->name = st->info->name;
1245 indio_dev->info = &ad4851_iio_info;
1246 indio_dev->modes = INDIO_DIRECT_MODE;
1247
1248 ret = st->info->parse_channels(indio_dev);
1249 if (ret)
1250 return ret;
1251
1252 ret = ad4851_scale_fill(indio_dev);
1253 if (ret)
1254 return ret;
1255
1256 st->back = devm_iio_backend_get(dev, NULL);
1257 if (IS_ERR(st->back))
1258 return PTR_ERR(st->back);
1259
1260 ret = devm_iio_backend_request_buffer(dev, st->back, indio_dev);
1261 if (ret)
1262 return ret;
1263
1264 ret = devm_iio_backend_enable(dev, st->back);
1265 if (ret)
1266 return ret;
1267
1268 ret = ad4851_calibrate(indio_dev);
1269 if (ret)
1270 return ret;
1271
1272 return devm_iio_device_register(dev, indio_dev);
1273 }
1274
1275 static const struct of_device_id ad4851_of_match[] = {
1276 { .compatible = "adi,ad4851", .data = &ad4851_info, },
1277 { .compatible = "adi,ad4852", .data = &ad4852_info, },
1278 { .compatible = "adi,ad4853", .data = &ad4853_info, },
1279 { .compatible = "adi,ad4854", .data = &ad4854_info, },
1280 { .compatible = "adi,ad4855", .data = &ad4855_info, },
1281 { .compatible = "adi,ad4856", .data = &ad4856_info, },
1282 { .compatible = "adi,ad4857", .data = &ad4857_info, },
1283 { .compatible = "adi,ad4858", .data = &ad4858_info, },
1284 { .compatible = "adi,ad4858i", .data = &ad4858i_info, },
1285 { }
1286 };
1287
1288 static const struct spi_device_id ad4851_spi_id[] = {
1289 { "ad4851", (kernel_ulong_t)&ad4851_info },
1290 { "ad4852", (kernel_ulong_t)&ad4852_info },
1291 { "ad4853", (kernel_ulong_t)&ad4853_info },
1292 { "ad4854", (kernel_ulong_t)&ad4854_info },
1293 { "ad4855", (kernel_ulong_t)&ad4855_info },
1294 { "ad4856", (kernel_ulong_t)&ad4856_info },
1295 { "ad4857", (kernel_ulong_t)&ad4857_info },
1296 { "ad4858", (kernel_ulong_t)&ad4858_info },
1297 { "ad4858i", (kernel_ulong_t)&ad4858i_info },
1298 { }
1299 };
1300 MODULE_DEVICE_TABLE(spi, ad4851_spi_id);
1301
1302 static struct spi_driver ad4851_driver = {
1303 .probe = ad4851_probe,
1304 .driver = {
1305 .name = "ad4851",
1306 .of_match_table = ad4851_of_match,
1307 },
1308 .id_table = ad4851_spi_id,
1309 };
1310 module_spi_driver(ad4851_driver);
1311
1312 MODULE_AUTHOR("Sergiu Cuciurean <sergiu.cuciurean@analog.com>");
1313 MODULE_AUTHOR("Dragos Bogdan <dragos.bogdan@analog.com>");
1314 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com>");
1315 MODULE_DESCRIPTION("Analog Devices AD4851 DAS driver");
1316 MODULE_LICENSE("GPL");
1317 MODULE_IMPORT_NS("IIO_BACKEND");
1318