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/src/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h59 virtual void MRI_NoteNewVirtualRegister(Register Reg) = 0;
60 virtual void MRI_NoteCloneVirtualRegister(Register NewReg, in MRI_NoteCloneVirtualRegister()
61 Register SrcReg) { in MRI_NoteCloneVirtualRegister()
104 IndexedMap<std::pair<unsigned, SmallVector<Register, 4>>,
114 MachineOperand *&getRegUseDefListHead(Register RegNo) { in getRegUseDefListHead()
120 MachineOperand *getRegUseDefListHead(Register RegNo) const { in getRegUseDefListHead()
150 std::vector<std::pair<MCRegister, Register>> LiveIns;
177 void noteNewVirtualRegister(Register Reg) { in noteNewVirtualRegister()
182 void noteCloneVirtualRegister(Register NewReg, Register SrcReg) { in noteCloneVirtualRegister()
230 bool shouldTrackSubRegLiveness(Register VReg) const { in shouldTrackSubRegLiveness()
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H A DVirtRegMap.h52 IndexedMap<Register, VirtReg2IndexFunctor> Virt2PhysMap;
99 bool hasPhys(Register virtReg) const { in hasPhys()
105 MCRegister getPhys(Register virtReg) const { in getPhys()
112 void assignVirt2Phys(Register virtReg, MCPhysReg physReg);
116 bool hasShape(Register virtReg) const { in hasShape()
120 ShapeT getShape(Register virtReg) const { in getShape()
125 void assignVirt2Shape(Register virtReg, ShapeT shape) { in assignVirt2Shape()
131 void clearVirt(Register virtReg) { in clearVirt()
145 bool hasPreferredPhys(Register VirtReg) const;
150 bool hasKnownPreference(Register VirtReg) const;
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H A DFunctionLoweringInfo.h74 Register DemoteRegister;
82 DenseMap<const Value *, Register> ValueMap;
89 DenseMap<Register, const Value*> VirtReg2Value;
93 const Value *getValueFromVirtualReg(Register Vreg);
96 DenseMap<const Value *, Register> CatchPadExceptionPointers;
119 Register Reg;
147 DenseMap<Register, Register> RegFixups;
149 DenseSet<Register> RegsWithFixups;
212 Register CreateReg(MVT VT, bool isDivergent = false);
214 Register CreateRegs(const Value *V);
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H A DLiveRangeEdit.h56 virtual bool LRE_CanEraseVirtReg(Register) { return true; } in LRE_CanEraseVirtReg() argument
59 virtual void LRE_WillShrinkVirtReg(Register) {} in LRE_WillShrinkVirtReg() argument
63 virtual void LRE_DidCloneVirtReg(Register New, Register Old) {} in LRE_DidCloneVirtReg()
68 SmallVectorImpl<Register> &NewRegs;
107 void MRI_NoteNewVirtualRegister(Register VReg) override;
114 LiveInterval &createEmptyIntervalFrom(Register OldReg, bool createSubRanges);
128 LiveRangeEdit(const LiveInterval *parent, SmallVectorImpl<Register> &newRegs,
145 Register getReg() const { return getParent().reg(); } in getReg()
148 using iterator = SmallVectorImpl<Register>::const_iterator;
153 Register get(unsigned idx) const { return NewRegs[idx + FirstNew]; } in get()
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/src/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h94 Register constrainRegToClass(MachineRegisterInfo &MRI,
96 const RegisterBankInfo &RBI, Register Reg,
107 Register constrainOperandRegClass(const MachineFunction &MF,
126 Register constrainOperandRegClass(const MachineFunction &MF,
150 bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI);
174 std::optional<APInt> getIConstantVRegVal(Register VReg,
178 std::optional<int64_t> getIConstantVRegSExtVal(Register VReg,
185 Register VReg;
191 getIConstantVRegValWithLookThrough(Register VReg,
198 Register VReg, const MachineRegisterInfo &MRI,
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H A DCombinerHelper.h56 Register Addr;
57 Register Base;
58 Register Offset;
66 Register Base;
71 Register Reg;
78 Register LogicNonShiftReg;
147 void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const;
152 Register ToReg) const;
163 const RegisterBank *getRegBank(Register Reg) const;
168 void setRegBank(Register Reg, const RegisterBank *RegBank);
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H A DCallLowering.h63 SmallVector<Register, 4> Regs;
67 SmallVector<Register, 2> OrigRegs;
81 ArgInfo(ArrayRef<Register> Regs, Type *Ty, unsigned OrigIndex,
94 ArgInfo(ArrayRef<Register> Regs, const Value &OrigValue, unsigned OrigIndex,
104 Register Discriminator;
123 Register SwiftErrorVReg;
126 Register ConvergenceCtrlToken;
154 Register DemoteRegister;
265 virtual Register getStackAddress(uint64_t MemSize, int64_t Offset,
281 virtual void assignValueToReg(Register ValVReg, Register PhysReg,
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H A DGISelKnownBits.h36 SmallDenseMap<Register, KnownBits, 16> ComputeKnownBitsCache;
38 void computeKnownBitsMin(Register Src0, Register Src1, KnownBits &Known,
42 unsigned computeNumSignBitsMin(Register Src0, Register Src1,
57 virtual void computeKnownBitsImpl(Register R, KnownBits &Known,
61 unsigned computeNumSignBits(Register R, const APInt &DemandedElts,
63 unsigned computeNumSignBits(Register R, unsigned Depth = 0);
66 KnownBits getKnownBits(Register R);
67 KnownBits getKnownBits(Register R, const APInt &DemandedElts,
72 APInt getKnownZeroes(Register R);
73 APInt getKnownOnes(Register R);
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H A DLegalizationArtifactCombiner.h61 SmallVectorImpl<Register> &UpdatedDefs, in tryCombineAnyExt()
67 Register DstReg = MI.getOperand(0).getReg(); in tryCombineAnyExt()
68 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineAnyExt()
71 Register TruncSrc; in tryCombineAnyExt()
85 Register ExtSrc; in tryCombineAnyExt()
120 SmallVectorImpl<Register> &UpdatedDefs, in tryCombineZExt()
126 Register DstReg = MI.getOperand(0).getReg(); in tryCombineZExt()
127 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineZExt()
131 Register TruncSrc; in tryCombineZExt()
132 Register SextSrc; in tryCombineZExt()
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/src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.h48 Register SrcReg, DenseMap<SDValue, Register> &VRBaseMap);
54 DenseMap<SDValue, Register> &VRBaseMap);
58 Register getVR(SDValue Op,
59 DenseMap<SDValue, Register> &VRBaseMap);
68 DenseMap<SDValue, Register> &VRBaseMap,
79 DenseMap<SDValue, Register> &VRBaseMap,
85 Register ConstrainForSubReg(Register VReg, unsigned SubIdx, MVT VT,
90 void EmitSubregNode(SDNode *Node, DenseMap<SDValue, Register> &VRBaseMap,
98 DenseMap<SDValue, Register> &VRBaseMap);
102 void EmitRegSequence(SDNode *Node, DenseMap<SDValue, Register> &VRBaseMap,
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/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILowerI1Copies.h26 Register Reg;
28 Register UpdatedReg;
30 Incoming(Register Reg, MachineBasicBlock *Block, Register UpdatedReg) in Incoming()
34 Register createLaneMaskReg(MachineRegisterInfo *MRI,
54 DenseSet<Register> PhiRegisters;
57 Register ExecReg;
67 bool isConstantLaneMask(Register Reg, bool &Val) const;
71 void initializeLaneMaskRegisterAttributes(Register LaneMask) { in initializeLaneMaskRegisterAttributes()
75 bool isLaneMaskReg(Register Reg) const { in isLaneMaskReg()
83 virtual void markAsLaneMask(Register DstReg) const = 0;
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H A DAMDGPULegalizerInfo.h40 Register getSegmentAperture(unsigned AddrSpace,
67 bool buildPCRelGlobalAddress(Register DstReg, LLT PtrTy, MachineIRBuilder &B,
71 void buildAbsGlobalAddress(Register DstReg, LLT PtrTy, MachineIRBuilder &B,
86 std::pair<Register, Register>
87 getScaledLogInput(MachineIRBuilder &B, Register Src, unsigned Flags) const;
91 bool legalizeFlogUnsafe(MachineIRBuilder &B, Register Dst, Register Src,
94 bool legalizeFExpUnsafe(MachineIRBuilder &B, Register Dst, Register Src,
104 void buildMultiply(LegalizerHelper &Helper, MutableArrayRef<Register> Accum,
105 ArrayRef<Register> Src0, ArrayRef<Register> Src1,
114 bool loadInputValue(Register DstReg, MachineIRBuilder &B,
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H A DAMDGPUGlobalISelDivergenceLowering.cpp65 Register buildRegCopyToLaneMask(Register Reg);
68 void markAsLaneMask(Register DstReg) const override;
74 void replaceDstReg(Register NewReg, Register OldReg,
78 Register DstReg, Register PrevReg,
79 Register CurReg) override;
89 void DivergenceLoweringHelper::markAsLaneMask(Register DstReg) const { in markAsLaneMask()
108 Register Dst = MI.getOperand(0).getReg(); in getCandidatesForLowering()
119 MI->getOperand(i + 1).getMBB(), Register()); in collectIncomingValuesFromPhi()
123 void DivergenceLoweringHelper::replaceDstReg(Register NewReg, Register OldReg, in replaceDstReg()
131 Register DivergenceLoweringHelper::buildRegCopyToLaneMask(Register Reg) { in buildRegCopyToLaneMask()
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H A DSIMachineFunctionInfo.h361 Register Reg;
366 PrologEpilogSGPRSaveRestoreInfo(SGPRSaveKind K, Register R)
368 Register getReg() const { return Reg; }
384 Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
388 Register FrameOffsetReg = AMDGPU::FP_REG;
393 Register StackPtrOffsetReg = AMDGPU::SP_REG;
398 Register LongBranchReservedReg;
486 void MRI_NoteNewVirtualRegister(Register Reg) override;
487 void MRI_NoteCloneVirtualRegister(Register NewReg, Register SrcReg) override;
507 SmallVector<Register, 2> SpillVGPRs;
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H A DAMDGPURegisterBankInfo.h48 bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const;
51 SmallSet<Register, 4> &SGPROperandRegs,
58 SmallSet<Register, 4> &SGPROperandRegs) const;
60 Register buildReadFirstLane(MachineIRBuilder &B, MachineRegisterInfo &MRI,
61 Register Src) const;
75 unsigned setBufferOffsets(MachineIRBuilder &B, Register CombinedOffset,
76 Register &VOffsetReg, Register &SOffsetReg,
90 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
91 Register Reg) const;
93 std::pair<Register, unsigned>
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H A DAMDGPUInstructionSelector.h72 bool isSGPR(Register Reg) const;
75 bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
78 Register Reg, const MachineRegisterInfo &MRI,
154 std::pair<Register, unsigned> selectVOP3ModsImpl(MachineOperand &Root,
159 Register copyToVGPRIfSrcFolded(Register Src, unsigned Mods,
184 std::pair<Register, unsigned>
185 selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI,
221 bool selectSmrdOffset(MachineOperand &Root, Register &Base, Register *SOffset,
232 std::pair<Register, int> selectFlatOffsetImpl(MachineOperand &Root,
247 bool checkFlatScratchSVSSwizzleBug(Register VAddr, Register SAddr,
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/src/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineSSAUpdater.cpp37 using AvailableValsTy = DenseMap<MachineBasicBlock *, Register>;
54 void MachineSSAUpdater::Initialize(Register V) { in Initialize()
71 void MachineSSAUpdater::AddAvailableValue(MachineBasicBlock *BB, Register V) { in AddAvailableValue()
77 Register MachineSSAUpdater::GetValueAtEndOfBlock(MachineBasicBlock *BB) { in GetValueAtEndOfBlock()
82 Register LookForIdenticalPHI(MachineBasicBlock *BB, in LookForIdenticalPHI()
83 SmallVectorImpl<std::pair<MachineBasicBlock *, Register>> &PredValues) { in LookForIdenticalPHI()
85 return Register(); in LookForIdenticalPHI()
89 return Register(); in LookForIdenticalPHI()
97 Register SrcReg = I->getOperand(i).getReg(); in LookForIdenticalPHI()
108 return Register(); in LookForIdenticalPHI()
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H A DRegAllocGreedy.h84 LiveRangeStage getStage(Register Reg) const { return Info[Reg].Stage; } in getStage()
90 void setStage(Register Reg, LiveRangeStage Stage) { in setStage()
101 LiveRangeStage getOrInitStage(Register Reg) { in getOrInitStage()
106 unsigned getCascade(Register Reg) const { return Info[Reg].Cascade; } in getCascade()
108 void setCascade(Register Reg, unsigned Cascade) { in setCascade()
113 unsigned getOrAssignNewCascade(Register Reg) { in getOrAssignNewCascade()
122 unsigned getCascadeOrCurrentNext(Register Reg) const { in getCascadeOrCurrentNext()
132 Register Reg = *Begin; in setStage()
138 void LRE_DidCloneVirtReg(Register New, Register Old);
296 SmallVectorImpl<Register> &) override;
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H A DMachineRegisterInfo.cpp59 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { in setRegClass()
64 void MachineRegisterInfo::setRegBank(Register Reg, in setRegBank()
70 constrainRegClass(MachineRegisterInfo &MRI, Register Reg, in constrainRegClass()
86 Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) { in constrainRegClass()
93 MachineRegisterInfo::constrainRegAttrs(Register Reg, in constrainRegAttrs()
94 Register ConstrainingReg, in constrainRegAttrs()
123 MachineRegisterInfo::recomputeRegClass(Register Reg) { in recomputeRegClass()
147 Register MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) { in createIncompleteVirtualRegister()
148 Register Reg = Register::index2VirtReg(getNumVirtRegs()); in createIncompleteVirtualRegister()
158 Register
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H A DTwoAddressInstructionPass.cpp115 DenseMap<Register, Register> SrcRegMap;
120 DenseMap<Register, Register> DstRegMap;
122 MachineInstr *getSingleDef(Register Reg, MachineBasicBlock *BB) const;
124 bool isRevCopyChain(Register FromReg, Register ToReg, int Maxlen);
126 bool noUseAfterLastDef(Register Reg, unsigned Dist, unsigned &LastDef);
128 bool isCopyToReg(MachineInstr &MI, Register &SrcReg, Register &DstReg,
132 bool isPlainlyKilled(const MachineInstr *MI, Register Reg) const;
135 bool isKilled(MachineInstr &MI, Register Reg, bool allowFalsePositives) const;
137 MachineInstr *findOnlyInterestingUse(Register Reg, MachineBasicBlock *MBB,
138 bool &IsCopy, Register &DstReg,
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/src/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVGlobalRegistry.h37 DenseMap<const MachineFunction *, DenseMap<Register, SPIRVType *>>
105 void add(const Constant *C, MachineFunction *MF, Register R) { in add()
109 void add(const GlobalVariable *GV, MachineFunction *MF, Register R) { in add()
113 void add(const Function *F, MachineFunction *MF, Register R) { in add()
117 void add(const Argument *Arg, MachineFunction *MF, Register R) { in add()
121 void add(const MachineInstr *MI, MachineFunction *MF, Register R) { in add()
125 Register find(const MachineInstr *MI, MachineFunction *MF) { in find()
129 Register find(const Constant *C, MachineFunction *MF) { in find()
133 Register find(const GlobalVariable *GV, MachineFunction *MF) { in find()
137 Register find(const Function *F, MachineFunction *MF) { in find()
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/src/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZMachineFunctionInfo.h35 Register VarArgsFirstGPR;
36 Register VarArgsFirstFPR;
42 Register VRegADA;
64 void setSpillGPRRegs(Register Low, Register High, unsigned Offs) { in setSpillGPRRegs()
74 void setRestoreGPRRegs(Register Low, Register High, unsigned Offs) { in setRestoreGPRRegs()
82 Register getVarArgsFirstGPR() const { return VarArgsFirstGPR; } in getVarArgsFirstGPR()
83 void setVarArgsFirstGPR(Register GPR) { VarArgsFirstGPR = GPR; } in setVarArgsFirstGPR()
86 Register getVarArgsFirstFPR() const { return VarArgsFirstFPR; } in getVarArgsFirstFPR()
87 void setVarArgsFirstFPR(Register FPR) { VarArgsFirstFPR = FPR; } in setVarArgsFirstFPR()
108 Register getADAVirtualRegister() const { return VRegADA; } in getADAVirtualRegister()
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/src/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCCallLowering.cpp38 void assignValueToReg(Register ValVReg, Register PhysReg,
40 void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
43 Register getStackAddress(uint64_t Size, int64_t Offset,
51 void OutgoingArgHandler::assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
54 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
58 void OutgoingArgHandler::assignValueToAddress(Register ValVReg, Register Addr, in assignValueToAddress()
65 Register OutgoingArgHandler::getStackAddress(uint64_t Size, int64_t Offset, in getStackAddress()
75 const Value *Val, ArrayRef<Register> VRegs, in lowerReturn()
77 Register SwiftErrorVReg) const { in lowerReturn()
116 ArrayRef<ArrayRef<Register>> VRegs, in lowerFormalArguments()
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/src/contrib/llvm-project/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp69 const Register ReservedRegs[] = { in getReservedRegs()
136 Register clobber;
146 inline MachineInstrBuilder build(const MCInstrDesc &MCID, Register DestReg) { in build()
149 inline MachineInstrBuilder build(unsigned InstOpc, Register DestReg) { in build()
162 void prepareReplaceFI(MachineInstr &MI, Register &FrameReg, int64_t &Offset,
167 void replaceFI(MachineInstr &MI, Register FrameReg, int64_t Offset,
171 void processSTQ(MachineInstr &MI, Register FrameReg, int64_t Offset,
173 void processLDQ(MachineInstr &MI, Register FrameReg, int64_t Offset,
176 void processSTVM(MachineInstr &MI, Register FrameReg, int64_t Offset,
178 void processLDVM(MachineInstr &MI, Register FrameReg, int64_t Offset,
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/src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp82 static Register buildLogBase2(Register V, MachineIRBuilder &MIB) { in buildLogBase2()
164 void CombinerHelper::replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, in replaceRegWith()
165 Register ToReg) const { in replaceRegWith()
178 Register ToReg) const { in replaceRegOpWith()
196 const RegisterBank *CombinerHelper::getRegBank(Register Reg) const { in getRegBank()
200 void CombinerHelper::setRegBank(Register Reg, const RegisterBank *RegBank) { in setRegBank()
215 Register DstReg = MI.getOperand(0).getReg(); in matchCombineCopy()
216 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineCopy()
220 Register DstReg = MI.getOperand(0).getReg(); in applyCombineCopy()
221 Register SrcReg = MI.getOperand(1).getReg(); in applyCombineCopy()
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