Lines Matching refs:Register
115 DenseMap<Register, Register> SrcRegMap;
120 DenseMap<Register, Register> DstRegMap;
122 MachineInstr *getSingleDef(Register Reg, MachineBasicBlock *BB) const;
124 bool isRevCopyChain(Register FromReg, Register ToReg, int Maxlen);
126 bool noUseAfterLastDef(Register Reg, unsigned Dist, unsigned &LastDef);
128 bool isCopyToReg(MachineInstr &MI, Register &SrcReg, Register &DstReg,
132 bool isPlainlyKilled(const MachineInstr *MI, Register Reg) const;
135 bool isKilled(MachineInstr &MI, Register Reg, bool allowFalsePositives) const;
137 MachineInstr *findOnlyInterestingUse(Register Reg, MachineBasicBlock *MBB,
138 bool &IsCopy, Register &DstReg,
141 bool regsAreCompatible(Register RegA, Register RegB) const;
144 DenseMap<Register, Register> &RegMap) const;
148 bool regOverlapsSet(const SmallVectorImpl<Register> &Set, Register Reg) const;
150 bool isProfitableToCommute(Register RegA, Register RegB, Register RegC,
156 bool isProfitableToConv3Addr(Register RegA, Register RegB);
159 MachineBasicBlock::iterator &nmi, Register RegA,
160 Register RegB, unsigned &Dist);
162 bool isDefTooClose(Register Reg, unsigned Dist, MachineInstr *MI);
165 MachineBasicBlock::iterator &nmi, Register Reg);
167 MachineBasicBlock::iterator &nmi, Register Reg);
179 void scanUses(Register DstReg);
298 TwoAddressInstructionImpl::getSingleDef(Register Reg, in getSingleDef()
319 bool TwoAddressInstructionImpl::isRevCopyChain(Register FromReg, Register ToReg, in isRevCopyChain()
321 Register TmpReg = FromReg; in isRevCopyChain()
339 bool TwoAddressInstructionImpl::noUseAfterLastDef(Register Reg, unsigned Dist, in noUseAfterLastDef()
362 bool TwoAddressInstructionImpl::isCopyToReg(MachineInstr &MI, Register &SrcReg, in isCopyToReg()
363 Register &DstReg, bool &IsSrcPhys, in isCopyToReg()
397 Register Reg) const { in isPlainlyKilled()
442 bool TwoAddressInstructionImpl::isKilled(MachineInstr &MI, Register Reg, in isKilled()
460 Register SrcReg, DstReg; in isKilled()
471 static bool isTwoAddrUse(MachineInstr &MI, Register Reg, Register &DstReg) { in isTwoAddrUse()
488 Register Reg, MachineBasicBlock *MBB, bool &IsCopy, Register &DstReg, in findOnlyInterestingUse()
502 Register SrcReg; in findOnlyInterestingUse()
530 static MCRegister getMappedReg(Register Reg, in getMappedReg()
531 DenseMap<Register, Register> &RegMap) { in getMappedReg() argument
533 DenseMap<Register, Register>::iterator SI = RegMap.find(Reg); in getMappedReg()
544 bool TwoAddressInstructionImpl::regsAreCompatible(Register RegA, in regsAreCompatible()
545 Register RegB) const { in regsAreCompatible()
555 const MachineOperand &MO, DenseMap<Register, Register> &RegMap) const { in removeMapRegEntry() argument
560 SmallVector<Register, 2> Srcs; in removeMapRegEntry()
562 Register ToReg = SI.second; in removeMapRegEntry()
567 Register Reg = MO.getReg(); in removeMapRegEntry()
598 Register Dst = MI->getOperand(0).getReg(); in removeClobberedSrcRegMap()
602 Register Src = MI->getOperand(1).getReg(); in removeClobberedSrcRegMap()
614 Register Reg = MO.getReg(); in removeClobberedSrcRegMap()
623 const SmallVectorImpl<Register> &Set, Register Reg) const { in regOverlapsSet()
633 bool TwoAddressInstructionImpl::isProfitableToCommute(Register RegA, in isProfitableToCommute()
634 Register RegB, in isProfitableToCommute()
635 Register RegC, in isProfitableToCommute()
743 Register RegC = MI->getOperand(RegCIdx).getReg(); in commuteInstruction()
760 Register RegA = MI->getOperand(DstIdx).getReg(); in commuteInstruction()
769 bool TwoAddressInstructionImpl::isProfitableToConv3Addr(Register RegA, in isProfitableToConv3Addr()
770 Register RegB) { in isProfitableToConv3Addr()
788 Register RegA, Register RegB, unsigned &Dist) { in convertInstTo3Addr()
828 void TwoAddressInstructionImpl::scanUses(Register DstReg) { in scanUses()
829 SmallVector<Register, 4> VirtRegPairs; in scanUses()
832 Register NewReg; in scanUses()
833 Register Reg = DstReg; in scanUses()
886 Register SrcReg, DstReg; in processCopy()
909 Register Reg) { in rescheduleMIBelowKill()
946 Register DstReg; in rescheduleMIBelowKill()
958 SmallVector<Register, 2> Uses; in rescheduleMIBelowKill()
959 SmallVector<Register, 2> Kills; in rescheduleMIBelowKill()
960 SmallVector<Register, 2> Defs; in rescheduleMIBelowKill()
964 Register MOReg = MO.getReg(); in rescheduleMIBelowKill()
1007 Register MOReg = MO.getReg(); in rescheduleMIBelowKill()
1074 bool TwoAddressInstructionImpl::isDefTooClose(Register Reg, unsigned Dist, in isDefTooClose()
1097 Register Reg) { in rescheduleKillAboveMI()
1129 Register DstReg; in rescheduleKillAboveMI()
1137 SmallVector<Register, 2> Uses; in rescheduleKillAboveMI()
1138 SmallVector<Register, 2> Kills; in rescheduleKillAboveMI()
1139 SmallVector<Register, 2> Defs; in rescheduleKillAboveMI()
1140 SmallVector<Register, 2> LiveDefs; in rescheduleKillAboveMI()
1144 Register MOReg = MO.getReg(); in rescheduleKillAboveMI()
1177 SmallVector<Register, 2> OtherDefs; in rescheduleKillAboveMI()
1181 Register MOReg = MO.getReg(); in rescheduleKillAboveMI()
1200 for (Register MOReg : OtherDefs) { in rescheduleKillAboveMI()
1256 Register DstOpReg = MI->getOperand(DstOpIdx).getReg(); in tryInstructionCommute()
1257 Register BaseOpReg = MI->getOperand(BaseOpIdx).getReg(); in tryInstructionCommute()
1269 Register OtherOpReg = MI->getOperand(OtherOpIdx).getReg(); in tryInstructionCommute()
1319 Register regA = MI.getOperand(DstIdx).getReg(); in tryInstructionTransform()
1320 Register regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1405 Register Reg = MRI->createVirtualRegister(RC); in tryInstructionTransform()
1472 SmallVector<Register, 4> OrigRegs; in tryInstructionTransform()
1526 Register SrcReg = SrcMO.getReg(); in collectTiedOperands()
1527 Register DstReg = DstMO.getReg(); in collectTiedOperands()
1564 Register RegB = 0; in processTiedPairs()
1571 Register RegA = DstMO.getReg(); in processTiedPairs()
1746 Register RegB = TO.first; in processStatepoint()
1756 Register RegA = DstMO.getReg(); in processStatepoint()
1888 Register SrcReg = mi->getOperand(SrcIdx).getReg(); in run()
1889 Register DstReg = mi->getOperand(DstIdx).getReg(); in run()
1931 Register Reg = mi->getOperand(0).getReg(); in run()
1986 Register DstReg = MI.getOperand(0).getReg(); in eliminateRegSequence()
1988 SmallVector<Register, 4> OrigRegs; in eliminateRegSequence()
2005 Register SrcReg = UseMO.getReg(); in eliminateRegSequence()