| /src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AllocationOrder.cpp | 30 const RegisterClassInfo &RegClassInfo, in create() argument
34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create()
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| H A D | BreakFalseDeps.cpp | 41 RegisterClassInfo RegClassInfo; member in llvm::BreakFalseDeps
156 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
289 RegClassInfo.runOnMachineFunction(mf); in runOnMachineFunction()
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| H A D | RegAllocEvictionAdvisor.cpp | 131 RegClassInfo(RA.getRegClassInfo()), RegCosts(TRI->getRegisterCosts(MF)), in RegAllocEvictionAdvisor()
235 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg())) < in canEvictInterferenceBasedOnCost()
236 RegClassInfo.getNumAllocatableRegs( in canEvictInterferenceBasedOnCost()
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| H A D | RegAllocBase.cpp | 66 RegClassInfo.runOnMachineFunction(vrm.getMachineFunction()); in init()
126 ArrayRef<MCPhysReg> AllocOrder = RegClassInfo.getOrder(RC); in allocatePhysRegs()
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| H A D | RegAllocBase.h | 71 RegisterClassInfo RegClassInfo; variable
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| H A D | RegAllocGreedy.cpp | 327 (2 * RegClassInfo.getNumAllocatableRegs(&RC))); in getPriority()
464 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix)) { in canReassign()
523 MCRegister CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg); in isUnusedCalleeSavedReg()
539 uint8_t MinCost = RegClassInfo.getMinCost(RC); in getOrderLimit()
549 OrderLimit = RegClassInfo.getLastCostChange(RC); in getOrderLimit()
566 << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI) in canAllocatePhysReg()
935 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); in splitAroundRegion()
1298 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); in tryBlockSplit()
1421 if (!RegClassInfo.isProperSubClass(CurRC)) { in tryInstructionSplit()
1442 RegClassInfo.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
[all …]
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| H A D | CriticalAntiDepBreaker.h | 41 const RegisterClassInfo &RegClassInfo; variable
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| H A D | RegAllocPriorityAdvisor.h | 43 const RegisterClassInfo &RegClassInfo; variable
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| H A D | RegAllocFast.cpp | 190 RegisterClassInfo RegClassInfo; member in __anonaa58e9000111::RegAllocFastImpl
938 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtReg()
993 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtRegUndef()
1072 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in defineVirtReg()
1163 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in useVirtReg()
1346 unsigned ClassSize0 = RegClassInfo.getOrder(&RC0).size(); in findAndSortDefOperandIndexes()
1347 unsigned ClassSize1 = RegClassInfo.getOrder(&RC1).size(); in findAndSortDefOperandIndexes()
1783 RegClassInfo.runOnMachineFunction(MF); in runOnMachineFunction()
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| H A D | PostRASchedulerList.cpp | 78 RegisterClassInfo RegClassInfo; member in __anonb369119d0111::PostRAScheduler
286 RegClassInfo.runOnMachineFunction(Fn); in runOnMachineFunction()
309 SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode, in runOnMachineFunction()
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| H A D | RegAllocPriorityAdvisor.cpp | 109 RegClassInfo(RA.getRegClassInfo()), Indexes(Indexes), in RegAllocPriorityAdvisor()
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| H A D | AllocationOrder.h | 85 const RegisterClassInfo &RegClassInfo,
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| H A D | AggressiveAntiDepBreaker.h | 122 const RegisterClassInfo &RegClassInfo; variable
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| H A D | MachineCombiner.cpp | 76 RegisterClassInfo RegClassInfo; member in __anond034810d0111::MachineCombiner
577 TII->shouldReduceRegisterPressure(MBB, &RegClassInfo); in combineInstructions()
737 RegClassInfo.runOnMachineFunction(MF); in runOnMachineFunction()
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| H A D | RegAllocEvictionAdvisor.h | 144 const RegisterClassInfo &RegClassInfo; variable
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| H A D | CriticalAntiDepBreaker.cpp | 44 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), in CriticalAntiDepBreaker()
399 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister()
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| H A D | RegAllocBasic.cpp | 262 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix); in selectOrSplit()
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| H A D | MachineScheduler.cpp | 209 RegClassInfo = new RegisterClassInfo(); in MachineSchedContext()
213 delete RegClassInfo; in ~MachineSchedContext()
458 RegClassInfo->runOnMachineFunction(*MF); in runOnMachineFunction()
1263 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, in initRegPressure()
1265 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd, in initRegPressure()
1317 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i); in initRegPressure()
1347 unsigned Limit = RegClassInfo->getRegPressureSetLimit(ID); in updateScheduledPressure()
1530 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd, in buildDAGWithRegPressure()
3292 unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs( in initPolicy()
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| H A D | AggressiveAntiDepBreaker.cpp | 124 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI) { in AggressiveAntiDepBreaker()
609 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
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| /src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPreAllocateWWMRegs.cpp | 45 RegisterClassInfo RegClassInfo; member in __anon40eb6bbc0111::SIPreAllocateWWMRegs
105 for (MCRegister PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { in processDef()
200 RegClassInfo.runOnMachineFunction(MF); in runOnMachineFunction()
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| H A D | SIMachineScheduler.h | 445 RPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, false, false); in initRPTracker()
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| /src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 242 struct RegClassInfo { struct
265 const RegClassInfo *const RCInfos; argument
274 const RegClassInfo *const RCIs,
800 const RegClassInfo &getRegClassInfo(const TargetRegisterClass &RC) const { in getRegClassInfo()
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| H A D | MachineScheduler.h | 136 RegisterClassInfo *RegClassInfo; member
400 RegisterClassInfo *RegClassInfo;
440 RegClassInfo(C->RegClassInfo), RPTracker(RegPressure), in ScheduleDAGMILive()
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| H A D | MachinePipeliner.h | 76 RegisterClassInfo RegClassInfo; variable
129 const RegisterClassInfo &RegClassInfo; variable
213 RegClassInfo(rci), II_setByPragma(II), LoopPipelinerInfo(PLI), in SwingSchedulerDAG()
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| H A D | VLIWMachineScheduler.h | 80 RegisterClassInfo *getRegClassInfo() { return RegClassInfo; } in getRegClassInfo()
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