1cf099d11SDimitry Andric //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
2cf099d11SDimitry Andric //
3e6d15924SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4e6d15924SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
5e6d15924SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6cf099d11SDimitry Andric //
7cf099d11SDimitry Andric //===----------------------------------------------------------------------===//
8cf099d11SDimitry Andric //
9cf099d11SDimitry Andric // This file implements an allocation order for virtual registers.
10cf099d11SDimitry Andric //
11cf099d11SDimitry Andric // The preferred allocation order for a virtual register depends on allocation
12cf099d11SDimitry Andric // hints and target hooks. The AllocationOrder class encapsulates all of that.
13cf099d11SDimitry Andric //
14cf099d11SDimitry Andric //===----------------------------------------------------------------------===//
15cf099d11SDimitry Andric
16cf099d11SDimitry Andric #include "AllocationOrder.h"
174a16efa3SDimitry Andric #include "llvm/CodeGen/MachineFunction.h"
18cf099d11SDimitry Andric #include "llvm/CodeGen/MachineRegisterInfo.h"
1958b69754SDimitry Andric #include "llvm/CodeGen/RegisterClassInfo.h"
204a16efa3SDimitry Andric #include "llvm/CodeGen/VirtRegMap.h"
214a16efa3SDimitry Andric #include "llvm/Support/Debug.h"
224a16efa3SDimitry Andric #include "llvm/Support/raw_ostream.h"
23cf099d11SDimitry Andric
24cf099d11SDimitry Andric using namespace llvm;
25cf099d11SDimitry Andric
265ca98fd9SDimitry Andric #define DEBUG_TYPE "regalloc"
275ca98fd9SDimitry Andric
28cf099d11SDimitry Andric // Compare VirtRegMap::getRegAllocPref().
create(unsigned VirtReg,const VirtRegMap & VRM,const RegisterClassInfo & RegClassInfo,const LiveRegMatrix * Matrix)29b60736ecSDimitry Andric AllocationOrder AllocationOrder::create(unsigned VirtReg, const VirtRegMap &VRM,
30dd58ef01SDimitry Andric const RegisterClassInfo &RegClassInfo,
31b60736ecSDimitry Andric const LiveRegMatrix *Matrix) {
324a16efa3SDimitry Andric const MachineFunction &MF = VRM.getMachineFunction();
334a16efa3SDimitry Andric const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
34b60736ecSDimitry Andric auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
35b60736ecSDimitry Andric SmallVector<MCPhysReg, 16> Hints;
36b60736ecSDimitry Andric bool HardHints =
37b60736ecSDimitry Andric TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix);
38cf099d11SDimitry Andric
39eb11fae6SDimitry Andric LLVM_DEBUG({
404a16efa3SDimitry Andric if (!Hints.empty()) {
414a16efa3SDimitry Andric dbgs() << "hints:";
42ac9a064cSDimitry Andric for (MCPhysReg Hint : Hints)
43ac9a064cSDimitry Andric dbgs() << ' ' << printReg(Hint, TRI);
444a16efa3SDimitry Andric dbgs() << '\n';
4556fe8f14SDimitry Andric }
464a16efa3SDimitry Andric });
47ac9a064cSDimitry Andric assert(all_of(Hints,
48ac9a064cSDimitry Andric [&](MCPhysReg Hint) { return is_contained(Order, Hint); }) &&
494a16efa3SDimitry Andric "Target hint is outside allocation order.");
50b60736ecSDimitry Andric return AllocationOrder(std::move(Hints), Order, HardHints);
51cf099d11SDimitry Andric }
52