Home
last modified time | relevance | path

Searched refs:PPC (Results 1 – 25 of 128) sorted by relevance

123456

/src/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCPredicates.cpp17 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { in InvertPredicate()
19 case PPC::PRED_EQ: return PPC::PRED_NE; in InvertPredicate()
20 case PPC::PRED_NE: return PPC::PRED_EQ; in InvertPredicate()
21 case PPC::PRED_LT: return PPC::PRED_GE; in InvertPredicate()
22 case PPC::PRED_GE: return PPC::PRED_LT; in InvertPredicate()
23 case PPC::PRED_GT: return PPC::PRED_LE; in InvertPredicate()
24 case PPC::PRED_LE: return PPC::PRED_GT; in InvertPredicate()
25 case PPC::PRED_NU: return PPC::PRED_UN; in InvertPredicate()
26 case PPC::PRED_UN: return PPC::PRED_NU; in InvertPredicate()
27 case PPC::PRED_EQ_MINUS: return PPC::PRED_NE_PLUS; in InvertPredicate()
[all …]
H A DPPCMCCodeEmitter.cpp55 ? (MCFixupKind)PPC::fixup_ppc_br24_notoc in getDirectBrEncoding()
56 : (MCFixupKind)PPC::fixup_ppc_br24))); in getDirectBrEncoding()
73 case PPC::BL8_NOTOC: in isNoTOCCallInstr()
74 case PPC::BL8_NOTOC_TLS: in isNoTOCCallInstr()
75 case PPC::BL8_NOTOC_RM: in isNoTOCCallInstr()
78 case PPC::BL8: in isNoTOCCallInstr()
79 case PPC::BL: in isNoTOCCallInstr()
80 case PPC::BL8_TLS: in isNoTOCCallInstr()
81 case PPC::BL_TLS: in isNoTOCCallInstr()
82 case PPC::BLA8: in isNoTOCCallInstr()
[all …]
H A DPPCMCTargetDesc.h17 #undef PPC
37 namespace PPC {
257 static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R); \
258 static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC::X); \
259 static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC::F); \
260 static const MCPhysReg FpRegs[16] = PPC_REGS_EVEN0_30(PPC::Fpair); \
261 static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC::VSRp); \
262 static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC::S); \
263 static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC::VF); \
264 static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V); \
[all …]
H A DPPCInstPrinter.cpp63 (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) && in printInst()
96 if (MI->getOpcode() == PPC::PLDpc) { in printInst()
114 if (MI->getOpcode() == PPC::RLWINM) { in printInst()
137 if (MI->getOpcode() == PPC::RLDICR || in printInst()
138 MI->getOpcode() == PPC::RLDICR_32) { in printInst()
163 if ((MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) && in printInst()
164 (!TT.isOSAIX() || STI.hasFeature(PPC::FeatureModernAIXAs))) { in printInst()
167 if (MI->getOpcode() == PPC::DCBTST) in printInst()
173 bool IsBookE = STI.hasFeature(PPC::FeatureBookE); in printInst()
188 if (MI->getOpcode() == PPC::DCBF) { in printInst()
[all …]
H A DPPCAsmBackend.cpp36 case PPC::fixup_ppc_nofixup: in adjustFixupValue()
38 case PPC::fixup_ppc_brcond14: in adjustFixupValue()
39 case PPC::fixup_ppc_brcond14abs: in adjustFixupValue()
41 case PPC::fixup_ppc_br24: in adjustFixupValue()
42 case PPC::fixup_ppc_br24abs: in adjustFixupValue()
43 case PPC::fixup_ppc_br24_notoc: in adjustFixupValue()
45 case PPC::fixup_ppc_half16: in adjustFixupValue()
47 case PPC::fixup_ppc_half16ds: in adjustFixupValue()
48 case PPC::fixup_ppc_half16dq: in adjustFixupValue()
50 case PPC::fixup_ppc_pcrel34: in adjustFixupValue()
[all …]
/src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp93 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP, in PPCInstrInfo()
95 STI.isPPC64() ? PPC::BLR8 : PPC::BLR), in PPCInstrInfo()
105 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 || in CreateTargetHazardRecognizer()
106 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) { in CreateTargetHazardRecognizer()
124 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8) in CreateTargetPostRAHazardRecognizer()
128 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 && in CreateTargetPostRAHazardRecognizer()
129 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) { in CreateTargetPostRAHazardRecognizer()
184 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || in getOperandLatency()
185 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); in getOperandLatency()
187 IsRegCR = PPC::CRRCRegClass.contains(Reg) || in getOperandLatency()
[all …]
H A DPPCRegisterInfo.cpp99 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR, in PPCRegisterInfo()
103 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; in PPCRegisterInfo()
104 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; in PPCRegisterInfo()
105 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; in PPCRegisterInfo()
106 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; in PPCRegisterInfo()
107 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; in PPCRegisterInfo()
108 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; in PPCRegisterInfo()
109 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; in PPCRegisterInfo()
110 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; in PPCRegisterInfo()
111 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32; in PPCRegisterInfo()
[all …]
H A DPPCInstrInfo.h102 #define NoInstr PPC::INSTRUCTION_LIST_END
105 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
106 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, \
107 PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, NoInstr, PPC::EVLDD, \
108 PPC::RESTORE_QUADWORD \
113 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
114 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
115 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, \
116 NoInstr, NoInstr, PPC::RESTORE_QUADWORD \
121 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
[all …]
H A DPPCVSXSwapRemoval.cpp168 return (isRegInClass(Reg, &PPC::VSRCRegClass) || in isVecReg()
169 isRegInClass(Reg, &PPC::VRRCRegClass)); in isVecReg()
174 return (isRegInClass(Reg, &PPC::VSFRCRegClass) || in isScalarVecReg()
175 isRegInClass(Reg, &PPC::VSSRCRegClass)); in isScalarVecReg()
288 case PPC::XXPERMDI: { in gatherVectorInstructions()
337 case PPC::LVX: in gatherVectorInstructions()
344 case PPC::LXVD2X: in gatherVectorInstructions()
345 case PPC::LXVW4X: in gatherVectorInstructions()
351 case PPC::LXSDX: in gatherVectorInstructions()
352 case PPC::LXSSPX: in gatherVectorInstructions()
[all …]
H A DPPCCallingConv.cpp34 static const MCPhysReg ELF64ArgGPRs[] = {PPC::X3, PPC::X4, PPC::X5, PPC::X6, in CC_PPC64_ELF_Shadow_GPR_Regs()
35 PPC::X7, PPC::X8, PPC::X9, PPC::X10}; in CC_PPC64_ELF_Shadow_GPR_Regs()
53 if ((State.AllocateReg(ELF64ArgGPRs) - PPC::X3) % 2 == 1) in CC_PPC64_ELF_Shadow_GPR_Regs()
73 PPC::R3, PPC::R4, PPC::R5, PPC::R6, in CC_PPC32_SVR4_Custom_AlignArgRegs()
74 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_AlignArgRegs()
98 PPC::R3, PPC::R4, PPC::R5, PPC::R6, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
99 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
123 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
124 PPC::F8 in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
133 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
[all …]
H A DPPCRegisterInfo.h28 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || in getCRFromCRBit()
29 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) in getCRFromCRBit()
30 Reg = PPC::CR0; in getCRFromCRBit()
31 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || in getCRFromCRBit()
32 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) in getCRFromCRBit()
33 Reg = PPC::CR1; in getCRFromCRBit()
34 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || in getCRFromCRBit()
35 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) in getCRFromCRBit()
36 Reg = PPC::CR2; in getCRFromCRBit()
37 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || in getCRFromCRBit()
[all …]
H A DPPCFastISel.cpp144 return RC->getID() == PPC::VSFRCRegClassID; in isVSFRCRegClass()
147 return RC->getID() == PPC::VSSRCRegClassID; in isVSSRCRegClass()
159 const PPC::Predicate Pred);
162 unsigned FP64LoadOpc = PPC::LFD);
200 static std::optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) { in getComparePred()
232 return PPC::PRED_EQ; in getComparePred()
237 return PPC::PRED_GT; in getComparePred()
242 return PPC::PRED_GE; in getComparePred()
247 return PPC::PRED_LT; in getComparePred()
252 return PPC::PRED_LE; in getComparePred()
[all …]
H A DPPCFrameLowering.cpp98 {PPC::F31, -8}, \ in getCalleeSavedSpillSlots()
99 {PPC::F30, -16}, \ in getCalleeSavedSpillSlots()
100 {PPC::F29, -24}, \ in getCalleeSavedSpillSlots()
101 {PPC::F28, -32}, \ in getCalleeSavedSpillSlots()
102 {PPC::F27, -40}, \ in getCalleeSavedSpillSlots()
103 {PPC::F26, -48}, \ in getCalleeSavedSpillSlots()
104 {PPC::F25, -56}, \ in getCalleeSavedSpillSlots()
105 {PPC::F24, -64}, \ in getCalleeSavedSpillSlots()
106 {PPC::F23, -72}, \ in getCalleeSavedSpillSlots()
107 {PPC::F22, -80}, \ in getCalleeSavedSpillSlots()
[all …]
H A DPPCMIPeephole.cpp148 BuildMI(MBB, At, At->getDebugLoc(), TII->get(PPC::IMPLICIT_DEF), Reg); in addDummyDef()
174 assert((MF.getRegInfo().use_empty(PPC::X2) || in runOnMachineFunction()
234 if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec || in getKnownLeadingZeroCount()
235 Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec) in getKnownLeadingZeroCount()
238 if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) && in getKnownLeadingZeroCount()
242 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec || in getKnownLeadingZeroCount()
243 Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec || in getKnownLeadingZeroCount()
244 Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) && in getKnownLeadingZeroCount()
248 if (Opcode == PPC::ANDI_rec) { in getKnownLeadingZeroCount()
253 if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZW_rec || in getKnownLeadingZeroCount()
[all …]
H A DPPCTLSDynamicCall.cpp68 bool IsTLSTPRelMI = MI.getOpcode() == PPC::GETtlsTpointer32AIX; in processBlock()
69 bool IsTLSLDAIXMI = (MI.getOpcode() == PPC::TLSLDAIX8 || in processBlock()
70 MI.getOpcode() == PPC::TLSLDAIX); in processBlock()
72 if (MI.getOpcode() != PPC::ADDItlsgdLADDR && in processBlock()
73 MI.getOpcode() != PPC::ADDItlsldLADDR && in processBlock()
74 MI.getOpcode() != PPC::ADDItlsgdLADDR32 && in processBlock()
75 MI.getOpcode() != PPC::ADDItlsldLADDR32 && in processBlock()
76 MI.getOpcode() != PPC::TLSGDAIX && in processBlock()
77 MI.getOpcode() != PPC::TLSGDAIX8 && !IsTLSTPRelMI && !IsPCREL && in processBlock()
83 if (MI.getOpcode() == PPC::ADJCALLSTACKDOWN) in processBlock()
[all …]
H A DPPCPreEmitPeephole.cpp61 case PPC::LBZ: in hasPCRelativeForm()
62 case PPC::LBZ8: in hasPCRelativeForm()
63 case PPC::LHA: in hasPCRelativeForm()
64 case PPC::LHA8: in hasPCRelativeForm()
65 case PPC::LHZ: in hasPCRelativeForm()
66 case PPC::LHZ8: in hasPCRelativeForm()
67 case PPC::LWZ: in hasPCRelativeForm()
68 case PPC::LWZ8: in hasPCRelativeForm()
69 case PPC::STB: in hasPCRelativeForm()
70 case PPC::STB8: in hasPCRelativeForm()
[all …]
H A DPPCISelDAGToDAG.cpp251 Align(4)) == PPC::AM_DSForm; in SelectDSForm()
259 Align(16)) == PPC::AM_DQForm; in SelectDQForm()
267 std::nullopt) == PPC::AM_DForm; in SelectDForm()
275 std::nullopt) == PPC::AM_PCRel; in SelectPCRelForm()
283 PPC::AM_PrefixDForm; in SelectPDForm()
290 std::nullopt) == PPC::AM_XForm; in SelectXForm()
298 PPC::AM_XForm; in SelectForceXForm()
476 GlobalBaseReg = PPC::R30; in INITIALIZE_PASS()
479 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MoveGOTtoLR)); in INITIALIZE_PASS()
480 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); in INITIALIZE_PASS()
[all …]
H A DPPCExpandAtomicPseudoInsts.cpp55 const MCInstrDesc &OR = TII->get(PPC::OR8); in PairedCopy()
56 const MCInstrDesc &XOR = TII->get(PPC::XOR8); in PairedCopy()
94 case PPC::ATOMIC_SWAP_I128: in expandMI()
95 case PPC::ATOMIC_LOAD_ADD_I128: in expandMI()
96 case PPC::ATOMIC_LOAD_SUB_I128: in expandMI()
97 case PPC::ATOMIC_LOAD_XOR_I128: in expandMI()
98 case PPC::ATOMIC_LOAD_NAND_I128: in expandMI()
99 case PPC::ATOMIC_LOAD_AND_I128: in expandMI()
100 case PPC::ATOMIC_LOAD_OR_I128: in expandMI()
102 case PPC::ATOMIC_CMP_SWAP_I128: in expandMI()
[all …]
H A DPPCAsmPrinter.cpp328 O << PPC::stripRegisterPrefix(RegName); in printOperand()
388 if (PPC::isVRRegister(Reg)) in PrintAsmOperand()
389 Reg = PPC::VSX32 + (Reg - PPC::V0); in PrintAsmOperand()
390 else if (PPC::isVFRegister(Reg)) in PrintAsmOperand()
391 Reg = PPC::VSX32 + (Reg - PPC::VF0); in PrintAsmOperand()
394 RegName = PPC::stripRegisterPrefix(RegName); in PrintAsmOperand()
538 MII->getOpcode() == PPC::DBG_VALUE || in LowerSTACKMAP()
548 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::NOP)); in LowerSTACKMAP()
572 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::LI8) in LowerPATCHPOINT()
576 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::RLDIC) in LowerPATCHPOINT()
[all …]
H A DPPCHazardRecognizers.cpp66 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR) in isBCTRAfterSet()
81 namespace llvm { namespace PPC { extern int getNonRecordFormOpcode(uint16_t); } } namespace
95 case PPC::Sched::IIC_IntDivW: in mustComeFirst()
96 case PPC::Sched::IIC_IntDivD: in mustComeFirst()
97 case PPC::Sched::IIC_LdStLoadUpd: in mustComeFirst()
98 case PPC::Sched::IIC_LdStLDU: in mustComeFirst()
99 case PPC::Sched::IIC_LdStLFDU: in mustComeFirst()
100 case PPC::Sched::IIC_LdStLFDUX: in mustComeFirst()
101 case PPC::Sched::IIC_LdStLHA: in mustComeFirst()
102 case PPC::Sched::IIC_LdStLHAU: in mustComeFirst()
[all …]
H A DPPCReduceCRLogicals.cpp158 OrigBROpcode == PPC::BC in splitMBB()
159 ? PPC::BCn in splitMBB()
160 : OrigBROpcode == PPC::BCn in splitMBB()
161 ? PPC::BC in splitMBB()
162 : OrigBROpcode == PPC::BCLR ? PPC::BCLRn : PPC::BCLR; in splitMBB()
225 TII->get(PPC::B)) in splitMBB()
274 if (BROp == PPC::BC || BROp == PPC::BCLR) { in computeBranchTargetAndInversion()
279 case PPC::CROR: in computeBranchTargetAndInversion()
284 case PPC::CRAND: in computeBranchTargetAndInversion()
289 case PPC::CRNAND: in computeBranchTargetAndInversion()
[all …]
H A DPPCCTRLoops.cpp110 assert((I.getOpcode() != PPC::DecreaseCTRloop && in runOnMachineFunction()
111 I.getOpcode() != PPC::DecreaseCTR8loop) && in runOnMachineFunction()
126 return MI->definesRegister(PPC::CTR, /*TRI=*/nullptr) || in isCTRClobber()
127 MI->definesRegister(PPC::CTR8, /*TRI=*/nullptr); in isCTRClobber()
130 if (MI->modifiesRegister(PPC::CTR, /*TRI=*/nullptr) || in isCTRClobber()
131 MI->modifiesRegister(PPC::CTR8, /*TRI=*/nullptr)) in isCTRClobber()
139 if (MI->readsRegister(PPC::CTR, /*TRI=*/nullptr) || in isCTRClobber()
140 MI->readsRegister(PPC::CTR8, /*TRI=*/nullptr)) in isCTRClobber()
159 return MI.getOpcode() == PPC::MTCTRloop || in processLoop()
160 MI.getOpcode() == PPC::MTCTR8loop; in processLoop()
[all …]
/src/contrib/llvm-project/clang/lib/Sema/
H A DSemaPPC.cpp59 case PPC::BI__builtin_divde: in isPPC_64Builtin()
60 case PPC::BI__builtin_divdeu: in isPPC_64Builtin()
61 case PPC::BI__builtin_bpermd: in isPPC_64Builtin()
62 case PPC::BI__builtin_pdepd: in isPPC_64Builtin()
63 case PPC::BI__builtin_pextd: in isPPC_64Builtin()
64 case PPC::BI__builtin_ppc_ldarx: in isPPC_64Builtin()
65 case PPC::BI__builtin_ppc_stdcx: in isPPC_64Builtin()
66 case PPC::BI__builtin_ppc_tdw: in isPPC_64Builtin()
67 case PPC::BI__builtin_ppc_trapd: in isPPC_64Builtin()
68 case PPC::BI__builtin_ppc_cmpeqb: in isPPC_64Builtin()
[all …]
/src/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp104 if (RB->getID() == PPC::GPRRegBankID) { in getRegClass()
106 return &PPC::G8RCRegClass; in getRegClass()
108 return &PPC::GPRCRegClass; in getRegClass()
110 if (RB->getID() == PPC::FPRRegBankID) { in getRegClass()
112 return &PPC::F4RCRegClass; in getRegClass()
114 return &PPC::F8RCRegClass; in getRegClass()
116 if (RB->getID() == PPC::VECRegBankID) { in getRegClass()
118 return &PPC::VSRCRegClass; in getRegClass()
120 if (RB->getID() == PPC::CRRegBankID) { in getRegClass()
122 return &PPC::CRBITRCRegClass; in getRegClass()
[all …]
H A DPPCRegisterBankInfo.cpp37 case PPC::G8RCRegClassID: in getRegBankFromRegClass()
38 case PPC::G8RC_NOX0RegClassID: in getRegBankFromRegClass()
39 case PPC::G8RC_and_G8RC_NOX0RegClassID: in getRegBankFromRegClass()
40 case PPC::GPRCRegClassID: in getRegBankFromRegClass()
41 case PPC::GPRC_NOR0RegClassID: in getRegBankFromRegClass()
42 case PPC::GPRC_and_GPRC_NOR0RegClassID: in getRegBankFromRegClass()
43 return getRegBank(PPC::GPRRegBankID); in getRegBankFromRegClass()
44 case PPC::VSFRCRegClassID: in getRegBankFromRegClass()
45 case PPC::SPILLTOVSRRC_and_VSFRCRegClassID: in getRegBankFromRegClass()
46 case PPC::SPILLTOVSRRC_and_VFRCRegClassID: in getRegBankFromRegClass()
[all …]

123456