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Searched refs:FIELD_PREP (Results 1 – 25 of 120) sorted by relevance

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/src/sys/dev/irdma/
H A Dirdma_uda.c62 FIELD_PREP(IRDMAQPC_MACADDRESS, irdma_mac_to_u64(info->mac_addr))); in irdma_sc_access_ah()
64 qw1 = FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_PDINDEXLO, info->pd_idx) | in irdma_sc_access_ah()
65 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_TC, info->tc_tos) | in irdma_sc_access_ah()
66 FIELD_PREP(IRDMA_UDAQPC_VLANTAG, info->vlan_tag); in irdma_sc_access_ah()
68 qw2 = FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ARPINDEX, info->dst_arpindex) | in irdma_sc_access_ah()
69 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_FLOWLABEL, info->flow_label) | in irdma_sc_access_ah()
70 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_HOPLIMIT, info->hop_ttl) | in irdma_sc_access_ah()
71 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_PDINDEXHI, info->pd_idx >> 16); in irdma_sc_access_ah()
75 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR0, info->dest_ip_addr[0]) | in irdma_sc_access_ah()
76 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR1, info->dest_ip_addr[1])); in irdma_sc_access_ah()
[all …]
H A Dirdma_ctrl.c281 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) | in irdma_sc_add_arp_cache_entry()
282 FIELD_PREP(IRDMA_CQPSQ_MAT_PERMANENT, info->permanent) | in irdma_sc_add_arp_cache_entry()
283 FIELD_PREP(IRDMA_CQPSQ_MAT_ENTRYVALID, true) | in irdma_sc_add_arp_cache_entry()
284 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); in irdma_sc_add_arp_cache_entry()
316 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) | in irdma_sc_del_arp_cache_entry()
317 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); in irdma_sc_del_arp_cache_entry()
351 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_APBVT) | in irdma_sc_manage_apbvt_entry()
352 FIELD_PREP(IRDMA_CQPSQ_MAPT_ADDPORT, info->add) | in irdma_sc_manage_apbvt_entry()
353 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); in irdma_sc_manage_apbvt_entry()
402 qw1 = FIELD_PREP(IRDMA_CQPSQ_QHASH_QPN, info->qp_num) | in irdma_sc_manage_qhash_table_entry()
[all …]
H A Dirdma_uk.c53 FIELD_PREP(IRDMAQPSQ_FRAG_TO, sge->addr)); in irdma_set_fragment()
55 FIELD_PREP(IRDMAQPSQ_VALID, valid) | in irdma_set_fragment()
56 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, sge->length) | in irdma_set_fragment()
57 FIELD_PREP(IRDMAQPSQ_FRAG_STAG, sge->lkey)); in irdma_set_fragment()
61 FIELD_PREP(IRDMAQPSQ_VALID, valid)); in irdma_set_fragment()
78 FIELD_PREP(IRDMAQPSQ_FRAG_TO, sge->addr)); in irdma_set_fragment_gen_1()
80 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, sge->length) | in irdma_set_fragment_gen_1()
81 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_STAG, sge->lkey)); in irdma_set_fragment_gen_1()
93 return FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_NOP) | in irdma_nop_hdr()
94 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, false) | in irdma_nop_hdr()
[all …]
H A Dirdma_puda.c132 offset24 = (offset24) ? 0 : FIELD_PREP(IRDMAQPSQ_VALID, 1); in irdma_puda_post_recvbuf()
138 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, buf->mem.size)); in irdma_puda_post_recvbuf()
141 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, buf->mem.size) | in irdma_puda_post_recvbuf()
493 hdr[1] = FIELD_PREP(IRDMA_UDA_QPSQ_OPCODE, IRDMA_OP_TYPE_SEND) | in irdma_puda_send()
494 FIELD_PREP(IRDMA_UDA_QPSQ_L4LEN, l4len) | in irdma_puda_send()
495 FIELD_PREP(IRDMAQPSQ_AHID, info->ah_id) | in irdma_puda_send()
496 FIELD_PREP(IRDMA_UDA_QPSQ_SIGCOMPL, 1) | in irdma_puda_send()
497 FIELD_PREP(IRDMA_UDA_QPSQ_VALID, in irdma_puda_send()
504 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, info->len) | in irdma_puda_send()
505 FIELD_PREP(IRDMA_UDA_QPSQ_VALID, qp->qp_uk.swqe_polarity)); in irdma_puda_send()
[all …]
/src/sys/contrib/dev/athk/ath11k/
H A Dhal_tx.c43 FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, ti->paddr); in ath11k_hal_tx_cmd_desc_setup()
45 FIELD_PREP(BUFFER_ADDR_INFO1_ADDR, in ath11k_hal_tx_cmd_desc_setup()
48 FIELD_PREP(BUFFER_ADDR_INFO1_RET_BUF_MGR, ti->rbm_id) | in ath11k_hal_tx_cmd_desc_setup()
49 FIELD_PREP(BUFFER_ADDR_INFO1_SW_COOKIE, ti->desc_id); in ath11k_hal_tx_cmd_desc_setup()
52 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_DESC_TYPE, ti->type) | in ath11k_hal_tx_cmd_desc_setup()
53 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE, ti->encap_type) | in ath11k_hal_tx_cmd_desc_setup()
54 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE, in ath11k_hal_tx_cmd_desc_setup()
56 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE, in ath11k_hal_tx_cmd_desc_setup()
58 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ADDR_EN, in ath11k_hal_tx_cmd_desc_setup()
60 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_CMD_NUM, in ath11k_hal_tx_cmd_desc_setup()
[all …]
H A Dhal_rx.c17 hdr->info0 = FIELD_PREP(HAL_DESC_HDR_INFO0_OWNER, owner) | in ath11k_hal_reo_set_desc_hdr()
18 FIELD_PREP(HAL_DESC_HDR_INFO0_BUF_TYPE, buffer_type); in ath11k_hal_reo_set_desc_hdr()
21 hdr->info0 |= FIELD_PREP(HAL_DESC_HDR_INFO0_DBG_RESERVED, magic); in ath11k_hal_reo_set_desc_hdr()
29 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_GET_QUEUE_STATS) | in ath11k_hal_reo_cmd_queue_stats()
30 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc)); in ath11k_hal_reo_cmd_queue_stats()
40 desc->info0 = FIELD_PREP(HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI, in ath11k_hal_reo_cmd_queue_stats()
61 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_FLUSH_CACHE) | in ath11k_hal_reo_cmd_flush_cache()
62 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc)); in ath11k_hal_reo_cmd_flush_cache()
72 desc->info0 = FIELD_PREP(HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI, in ath11k_hal_reo_cmd_flush_cache()
81 FIELD_PREP(HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX, in ath11k_hal_reo_cmd_flush_cache()
[all …]
H A Dwmi.c313 cmd |= FIELD_PREP(WMI_CMD_HDR_CMD_ID, cmd_id); in ath11k_wmi_cmd_send_nowait()
725 cmd->tlv_header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_MGMT_TX_SEND_CMD) | in ath11k_wmi_mgmt_send()
726 FIELD_PREP(WMI_TLV_LEN, sizeof(*cmd) - TLV_HDR_SIZE); in ath11k_wmi_mgmt_send()
737 frame_tlv->header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_ARRAY_BYTE) | in ath11k_wmi_mgmt_send()
738 FIELD_PREP(WMI_TLV_LEN, buf_len); in ath11k_wmi_mgmt_send()
783 cmd->tlv_header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_VDEV_CREATE_CMD) | in ath11k_wmi_vdev_create()
784 FIELD_PREP(WMI_TLV_LEN, sizeof(*cmd) - TLV_HDR_SIZE); in ath11k_wmi_vdev_create()
804 tlv->header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_ARRAY_STRUCT) | in ath11k_wmi_vdev_create()
805 FIELD_PREP(WMI_TLV_LEN, len); in ath11k_wmi_vdev_create()
815 FIELD_PREP(WMI_TLV_TAG, WMI_TAG_VDEV_TXRX_STREAMS) | in ath11k_wmi_vdev_create()
[all …]
H A Ddp_tx.c148 ti.desc_id = FIELD_PREP(DP_TX_DESC_ID_MAC_ID, ar->pdev_idx) | in ath11k_dp_tx()
149 FIELD_PREP(DP_TX_DESC_ID_MSDU_ID, ret) | in ath11k_dp_tx()
150 FIELD_PREP(DP_TX_DESC_ID_POOL_ID, pool_id); in ath11k_dp_tx()
157 ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TO_FW, 1); in ath11k_dp_tx()
185 ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN, 1) | in ath11k_dp_tx()
186 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN, 1) | in ath11k_dp_tx()
187 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN, 1) | in ath11k_dp_tx()
188 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN, 1) | in ath11k_dp_tx()
189 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN, 1); in ath11k_dp_tx()
195 ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE, 1); in ath11k_dp_tx()
[all …]
H A Dhal.c267 val |= FIELD_PREP(HAL_CE_DST_R0_DEST_CTRL_MAX_LEN, in ath11k_hal_ce_dst_setup()
287 val = FIELD_PREP(HAL_REO1_RING_MSI1_BASE_MSB_ADDR, in ath11k_hal_srng_dst_hw_init()
301 val = FIELD_PREP(HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB, in ath11k_hal_srng_dst_hw_init()
304 FIELD_PREP(HAL_REO1_RING_BASE_MSB_RING_SIZE, in ath11k_hal_srng_dst_hw_init()
308 val = FIELD_PREP(HAL_REO1_RING_ID_RING_ID, srng->ring_id) | in ath11k_hal_srng_dst_hw_init()
309 FIELD_PREP(HAL_REO1_RING_ID_ENTRY_SIZE, srng->entry_size); in ath11k_hal_srng_dst_hw_init()
313 val = FIELD_PREP(HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD, in ath11k_hal_srng_dst_hw_init()
316 val |= FIELD_PREP(HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD, in ath11k_hal_srng_dst_hw_init()
366 val = FIELD_PREP(HAL_TCL1_RING_MSI1_BASE_MSB_ADDR, in ath11k_hal_srng_src_hw_init()
381 val = FIELD_PREP(HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB, in ath11k_hal_srng_src_hw_init()
[all …]
/src/sys/contrib/dev/mediatek/mt76/mt7603/
H A Dinit.c28 [1] = FIELD_PREP(MT_TXD3_REM_TX_COUNT, 0xf), in mt7603_set_tmac_template()
61 FIELD_PREP(MT_PSE_FRP_P0, 7) | in mt7603_dma_sched_init()
62 FIELD_PREP(MT_PSE_FRP_P1, 6) | in mt7603_dma_sched_init()
63 FIELD_PREP(MT_PSE_FRP_P2_RQ2, 4)); in mt7603_dma_sched_init()
123 (FIELD_PREP(MT_WF_RMAC_RMCR_SMPS_MODE, 3) | in mt7603_phy_init()
124 FIELD_PREP(MT_WF_RMAC_RMCR_RX_STREAMS, rx_chains))); in mt7603_phy_init()
153 FIELD_PREP(MT_AGG_LIMIT_AC(0), 24) | in mt7603_mac_init()
154 FIELD_PREP(MT_AGG_LIMIT_AC(1), 24) | in mt7603_mac_init()
155 FIELD_PREP(MT_AGG_LIMIT_AC(2), 24) | in mt7603_mac_init()
156 FIELD_PREP(MT_AGG_LIMIT_AC(3), 24)); in mt7603_mac_init()
[all …]
H A Dmac.c47 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | in mt7603_mac_set_timing()
48 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); in mt7603_mac_set_timing()
49 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | in mt7603_mac_set_timing()
50 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 24); in mt7603_mac_set_timing()
52 u32 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | in mt7603_mac_set_timing()
53 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); in mt7603_mac_set_timing()
70 FIELD_PREP(MT_IFS_EIFS, 360) | in mt7603_mac_set_timing()
71 FIELD_PREP(MT_IFS_RIFS, 2) | in mt7603_mac_set_timing()
72 FIELD_PREP(MT_IFS_SIFS, sifs) | in mt7603_mac_set_timing()
73 FIELD_PREP(MT_IFS_SLOT, dev->slottime)); in mt7603_mac_set_timing()
[all …]
/src/sys/contrib/dev/mediatek/mt76/mt76x2/
H A Dusb_phy.c64 [0] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 0) | in mt76x2u_phy_set_channel()
65 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 1) | in mt76x2u_phy_set_channel()
66 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | in mt76x2u_phy_set_channel()
67 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | in mt76x2u_phy_set_channel()
68 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(0)), in mt76x2u_phy_set_channel()
69 [1] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 1) | in mt76x2u_phy_set_channel()
70 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 0) | in mt76x2u_phy_set_channel()
71 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | in mt76x2u_phy_set_channel()
72 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | in mt76x2u_phy_set_channel()
73 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(1)), in mt76x2u_phy_set_channel()
[all …]
H A Dpci_phy.c126 [0] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 0) | in mt76x2_phy_set_channel()
127 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 1) | in mt76x2_phy_set_channel()
128 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | in mt76x2_phy_set_channel()
129 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | in mt76x2_phy_set_channel()
130 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(0)), in mt76x2_phy_set_channel()
131 [1] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 1) | in mt76x2_phy_set_channel()
132 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 0) | in mt76x2_phy_set_channel()
133 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | in mt76x2_phy_set_channel()
134 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | in mt76x2_phy_set_channel()
135 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(1)), in mt76x2_phy_set_channel()
[all …]
H A Dinit.c86 (FIELD_PREP(MT_PROT_CFG_RATE, 0x3) | \ in mt76_write_mac_initvals()
87 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \ in mt76_write_mac_initvals()
88 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \ in mt76_write_mac_initvals()
92 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \ in mt76_write_mac_initvals()
93 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \ in mt76_write_mac_initvals()
94 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \ in mt76_write_mac_initvals()
98 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \ in mt76_write_mac_initvals()
99 FIELD_PREP(MT_PROT_CFG_CTRL, 1) | \ in mt76_write_mac_initvals()
100 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \ in mt76_write_mac_initvals()
101 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x17)) in mt76_write_mac_initvals()
[all …]
/src/contrib/ofed/libirdma/
H A Dirdma_uk.c53 FIELD_PREP(IRDMAQPSQ_FRAG_TO, sge->addr)); in irdma_set_fragment()
55 FIELD_PREP(IRDMAQPSQ_VALID, valid) | in irdma_set_fragment()
56 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, sge->length) | in irdma_set_fragment()
57 FIELD_PREP(IRDMAQPSQ_FRAG_STAG, sge->lkey)); in irdma_set_fragment()
61 FIELD_PREP(IRDMAQPSQ_VALID, valid)); in irdma_set_fragment()
78 FIELD_PREP(IRDMAQPSQ_FRAG_TO, sge->addr)); in irdma_set_fragment_gen_1()
80 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, sge->length) | in irdma_set_fragment_gen_1()
81 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_STAG, sge->lkey)); in irdma_set_fragment_gen_1()
93 return FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_NOP) | in irdma_nop_hdr()
94 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, false) | in irdma_nop_hdr()
[all …]
/src/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dusb_sdio.c76 w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, rate->bw); in mt7663_usb_sdio_set_rates()
83 w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, rate->bw) | in mt7663_usb_sdio_set_rates()
84 FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE, in mt7663_usb_sdio_set_rates()
90 FIELD_PREP(MT_WTBL_RIUCR1_RATE0, rate->probe_val) | in mt7663_usb_sdio_set_rates()
91 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, rate->val[0]) | in mt7663_usb_sdio_set_rates()
92 FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, rate->val[1])); in mt7663_usb_sdio_set_rates()
95 FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, rate->val[1] >> 8) | in mt7663_usb_sdio_set_rates()
96 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, rate->val[1]) | in mt7663_usb_sdio_set_rates()
97 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, rate->val[2]) | in mt7663_usb_sdio_set_rates()
98 FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, rate->val[2])); in mt7663_usb_sdio_set_rates()
[all …]
H A Dinit.c93 FIELD_PREP(MT_TMAC_TRCR_CCA_SEL, 2) | in mt7615_init_mac_chain()
94 FIELD_PREP(MT_TMAC_TRCR_SEC_CCA_SEL, 0)); in mt7615_init_mac_chain()
98 FIELD_PREP(MT_AGG_ACR_CFEND_RATE, MT7615_CFEND_RATE_DEFAULT) | in mt7615_init_mac_chain()
99 FIELD_PREP(MT_AGG_ACR_BAR_RATE, MT7615_BAR_RATE_DEFAULT)); in mt7615_init_mac_chain()
102 FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), 7) | in mt7615_init_mac_chain()
103 FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), 2) | in mt7615_init_mac_chain()
104 FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), 2) | in mt7615_init_mac_chain()
105 FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), 2) | in mt7615_init_mac_chain()
106 FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), 1) | in mt7615_init_mac_chain()
107 FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), 1) | in mt7615_init_mac_chain()
[all …]
H A Ddma.c149 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) | in mt7622_dma_sched_init()
150 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8)); in mt7622_dma_sched_init()
154 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x10) | in mt7622_dma_sched_init()
155 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800)); in mt7622_dma_sched_init()
172 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) | in mt7663_dma_sched_init()
173 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8)); in mt7663_dma_sched_init()
183 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x40) | in mt7663_dma_sched_init()
184 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800)); in mt7663_dma_sched_init()
186 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x40) | in mt7663_dma_sched_init()
187 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x40)); in mt7663_dma_sched_init()
[all …]
H A Dmac.c143 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | in mt7615_mac_set_timing()
144 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); in mt7615_mac_set_timing()
145 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | in mt7615_mac_set_timing()
146 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); in mt7615_mac_set_timing()
175 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | in mt7615_mac_set_timing()
176 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); in mt7615_mac_set_timing()
181 FIELD_PREP(MT_IFS_EIFS, 360) | in mt7615_mac_set_timing()
182 FIELD_PREP(MT_IFS_RIFS, 2) | in mt7615_mac_set_timing()
183 FIELD_PREP(MT_IFS_SIFS, sifs) | in mt7615_mac_set_timing()
184 FIELD_PREP(MT_IFS_SLOT, phy->slottime)); in mt7615_mac_set_timing()
[all …]
/src/sys/contrib/dev/mediatek/mt76/
H A Dmt76_connac_mac.c20 he_ppet[0] = FIELD_PREP(IEEE80211_PPE_THRES_NSS_MASK, nss - 1) | in mt76_connac_gen_ppe_thresh()
21 FIELD_PREP(IEEE80211_PPE_THRES_RU_INDEX_BITMASK_MASK, in mt76_connac_gen_ppe_thresh()
354 return FIELD_PREP(MT_TX_RATE_NSS, nss) | in mt76_connac2_mac_tx_rate_val()
355 FIELD_PREP(MT_TX_RATE_IDX, rateidx) | in mt76_connac2_mac_tx_rate_val()
356 FIELD_PREP(MT_TX_RATE_MODE, mode); in mt76_connac2_mac_tx_rate_val()
377 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3) | in mt76_connac2_mac_write_txwi_8023()
378 FIELD_PREP(MT_TXD1_TID, tid); in mt76_connac2_mac_write_txwi_8023()
389 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | in mt76_connac2_mac_write_txwi_8023()
390 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype); in mt76_connac2_mac_write_txwi_8023()
394 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) | in mt76_connac2_mac_write_txwi_8023()
[all …]
H A Dmt792x_mac.c43 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | in mt792x_mac_set_timeing()
44 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); in mt792x_mac_set_timeing()
45 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | in mt792x_mac_set_timeing()
46 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); in mt792x_mac_set_timeing()
58 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | in mt792x_mac_set_timeing()
59 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); in mt792x_mac_set_timeing()
64 FIELD_PREP(MT_IFS_EIFS, 360) | in mt792x_mac_set_timeing()
65 FIELD_PREP(MT_IFS_RIFS, 2) | in mt792x_mac_set_timeing()
66 FIELD_PREP(MT_IFS_SIFS, sifs) | in mt792x_mac_set_timeing()
67 FIELD_PREP(MT_IFS_SLOT, phy->slottime)); in mt792x_mac_set_timeing()
[all …]
H A Dmt792x_usb.c130 FIELD_PREP(MT_WPDMA0_MAX_CNT_MASK, (_cnt_)) | \ in mt792xu_dma_prefetch()
131 FIELD_PREP(MT_WPDMA0_BASE_PTR_MASK, (_base_))) in mt792xu_dma_prefetch()
160 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) | in mt792xu_wfdma_init()
161 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 0)); in mt792xu_wfdma_init()
164 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x3) | in mt792xu_wfdma_init()
165 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0xfff)); in mt792xu_wfdma_init()
168 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x0) | in mt792xu_wfdma_init()
169 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x0)); in mt792xu_wfdma_init()
/src/sys/dev/qat/qat_common/
H A Dadf_pfvf_vf_proto.c15 #define FIELD_PREP(_mask, _val) \ macro
135 blk_type = FIELD_PREP(ADF_VF2PF_SMALL_BLOCK_TYPE_MASK, *type); in adf_vf2pf_blkmsg_data_req()
136 blk_byte = FIELD_PREP(ADF_VF2PF_SMALL_BLOCK_BYTE_MASK, *data); in adf_vf2pf_blkmsg_data_req()
140 blk_type = FIELD_PREP(ADF_VF2PF_MEDIUM_BLOCK_TYPE_MASK, in adf_vf2pf_blkmsg_data_req()
142 blk_byte = FIELD_PREP(ADF_VF2PF_MEDIUM_BLOCK_BYTE_MASK, *data); in adf_vf2pf_blkmsg_data_req()
146 blk_type = FIELD_PREP(ADF_VF2PF_LARGE_BLOCK_TYPE_MASK, in adf_vf2pf_blkmsg_data_req()
148 blk_byte = FIELD_PREP(ADF_VF2PF_LARGE_BLOCK_BYTE_MASK, *data); in adf_vf2pf_blkmsg_data_req()
170 blk_type | blk_byte | FIELD_PREP(ADF_VF2PF_BLOCK_CRC_REQ_MASK, crc); in adf_vf2pf_blkmsg_data_req()
/src/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dsoc.c123 val = FIELD_PREP(MT_ADIE_EFUSE_MODE_MASK, 0) | in mt7986_wmac_adie_efuse_read()
124 FIELD_PREP(MT_ADIE_EFUSE_ADDR_MASK, addr) | in mt7986_wmac_adie_efuse_read()
125 FIELD_PREP(MT_ADIE_EFUSE_KICK_MASK, 1); in mt7986_wmac_adie_efuse_read()
191 FIELD_PREP(MT_TOP_POS_FAST_EN_MASK, 0x1)); in mt7986_wmac_consys_reset()
239 FIELD_PREP(MT_INFRACFG_RX_EN_MASK, enable)); in mt7986_wmac_consys_lockup()
248 FIELD_PREP(MT_INFRACFG_TX_EN_MASK, enable)); in mt7986_wmac_consys_lockup()
257 FIELD_PREP(MT_INFRACFG_RX_EN_MASK, enable)); in mt7986_wmac_consys_lockup()
260 FIELD_PREP(MT_INFRACFG_TX_EN_MASK, enable)); in mt7986_wmac_consys_lockup()
391 FIELD_PREP(MT_ADIE_VRPI_SEL_CR_MASK, val)); in mt7986_wmac_adie_thermal_cal()
398 FIELD_PREP(MT_ADIE_PGA_GAIN_MASK, val)); in mt7986_wmac_adie_thermal_cal()
[all …]
/src/sys/contrib/dev/rtw89/
H A Dcore.c1426 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) | in rtw89_build_txwd_body0()
1427 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | in rtw89_build_txwd_body0()
1428 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | in rtw89_build_txwd_body0()
1429 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | in rtw89_build_txwd_body0()
1430 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | in rtw89_build_txwd_body0()
1431 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) | in rtw89_build_txwd_body0()
1432 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) | in rtw89_build_txwd_body0()
1433 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode); in rtw89_build_txwd_body0()
1440 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | in rtw89_build_txwd_body0_v1()
1441 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | in rtw89_build_txwd_body0_v1()
[all …]

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