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Searched refs:xl (Results 1 – 12 of 12) sorted by relevance

/qemu/target/riscv/
H A Dcpu.h236 uint32_t xl; /* current xlen */ member
718 RISCVMXL xl = env->misa_mxl; in cpu_get_xl() local
725 if (xl != MXL_RV32) { in cpu_get_xl()
730 xl = get_field(env->mstatus, MSTATUS64_UXL); in cpu_get_xl()
733 xl = get_field(env->mstatus, MSTATUS64_SXL); in cpu_get_xl()
737 return xl; in cpu_get_xl()
760 return env->xl; in cpu_address_xl()
771 return 16 << env->xl; in riscv_cpu_xlen()
H A Dtranslate.c62 RISCVMXL xl; member
133 #define get_xl(ctx) ((ctx)->xl)
1280 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); in riscv_tr_init_disas_context()
1324 ctx->ol = ctx->xl; in riscv_tr_translate_insn()
H A Dgdbstub.c92 if (env->xl < MXL_RV64) { in riscv_cpu_gdb_write_register()
H A Dcsr.c913 switch (env->xl) { in read_vtype()
1887 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) in add_status_sd() argument
1892 switch (xl) { in add_status_sd()
1981 RISCVMXL xl = riscv_cpu_mxl(env); in write_mstatus() local
2019 if (xl != MXL_RV32 || env->debugger) { in write_mstatus()
2042 env->xl = cpu_recompute_xl(env); in write_mstatus()
2172 env->xl = riscv_cpu_mxl(env); in write_misa()
3850 if (env->xl != MXL_RV32 || env->debugger) { in read_sstatus_i128()
3869 if (env->xl != MXL_RV32 || env->debugger) { in read_sstatus()
3889 if (env->xl != MXL_RV32 || env->debugger) { in write_sstatus()
H A Dmachine.c258 env->xl = cpu_recompute_xl(env); in riscv_cpu_post_load()
H A Dcpu.c646 if (env->xl == MXL_RV32) { in riscv_cpu_set_pc()
659 if (env->xl == MXL_RV32) { in riscv_cpu_get_pc()
774 env->xl = riscv_cpu_mxl(env); in riscv_cpu_reset_hold()
813 switch (env->xl) { in riscv_cpu_disas_set_info()
H A Dop_helper.c73 target_ulong mask = env->xl == MXL_RV32 ? UINT32_MAX : (target_ulong)-1; in helper_csrw()
H A Dcpu_helper.c1045 env->xl = cpu_recompute_xl(env); in riscv_cpu_set_mode()
/qemu/linux-user/riscv/
H A Dtarget_proc.h19 mmu = (cpu_env->xl == MXL_RV32) ? "sv32" : "sv48"; in open_cpuinfo()
/qemu/target/riscv/tcg/
H A Dtcg-cpu.c187 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); in riscv_get_tb_cpu_state()
193 .pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc, in riscv_get_tb_cpu_state()
204 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); in riscv_cpu_synchronize_from_tb() local
208 if (xl == MXL_RV32) { in riscv_cpu_synchronize_from_tb()
222 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); in riscv_restore_state_to_opc() local
231 if (xl == MXL_RV32) { in riscv_restore_state_to_opc()
/qemu/tests/qemu-iotests/tests/
H A Dparallels-checks82 fallocate -xl $((file_size + CLUSTER_SIZE)) "$TEST_IMG"
/qemu/target/riscv/insn_trans/
H A Dtrans_rvi.c.inc1048 RISCVMXL xl = get_xl(ctx);
1049 if (xl < MXL_RV128) {
1060 TCGv mask = tcg_constant_tl(xl == MXL_RV32 ? UINT32_MAX :
1139 RISCVMXL xl = get_xl(ctx);
1140 if (xl < MXL_RV128) {
1151 TCGv mask = tcg_constant_tl(xl == MXL_RV32 ? UINT32_MAX :