1*121c8dd6SRichard Henderson /*
2*121c8dd6SRichard Henderson * RISC-V specific proc functions for linux-user
3*121c8dd6SRichard Henderson *
4*121c8dd6SRichard Henderson * SPDX-License-Identifier: GPL-2.0-or-later
5*121c8dd6SRichard Henderson */
6*121c8dd6SRichard Henderson #ifndef RISCV_TARGET_PROC_H
7*121c8dd6SRichard Henderson #define RISCV_TARGET_PROC_H
8*121c8dd6SRichard Henderson
open_cpuinfo(CPUArchState * cpu_env,int fd)9*121c8dd6SRichard Henderson static int open_cpuinfo(CPUArchState *cpu_env, int fd)
10*121c8dd6SRichard Henderson {
11*121c8dd6SRichard Henderson int i;
12*121c8dd6SRichard Henderson int num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
13*121c8dd6SRichard Henderson RISCVCPU *cpu = env_archcpu(cpu_env);
14*121c8dd6SRichard Henderson const RISCVCPUConfig *cfg = riscv_cpu_cfg((CPURISCVState *) cpu_env);
15*121c8dd6SRichard Henderson char *isa_string = riscv_isa_string(cpu);
16*121c8dd6SRichard Henderson const char *mmu;
17*121c8dd6SRichard Henderson
18*121c8dd6SRichard Henderson if (cfg->mmu) {
19*121c8dd6SRichard Henderson mmu = (cpu_env->xl == MXL_RV32) ? "sv32" : "sv48";
20*121c8dd6SRichard Henderson } else {
21*121c8dd6SRichard Henderson mmu = "none";
22*121c8dd6SRichard Henderson }
23*121c8dd6SRichard Henderson
24*121c8dd6SRichard Henderson for (i = 0; i < num_cpus; i++) {
25*121c8dd6SRichard Henderson dprintf(fd, "processor\t: %d\n", i);
26*121c8dd6SRichard Henderson dprintf(fd, "hart\t\t: %d\n", i);
27*121c8dd6SRichard Henderson dprintf(fd, "isa\t\t: %s\n", isa_string);
28*121c8dd6SRichard Henderson dprintf(fd, "mmu\t\t: %s\n", mmu);
29*121c8dd6SRichard Henderson dprintf(fd, "uarch\t\t: qemu\n\n");
30*121c8dd6SRichard Henderson }
31*121c8dd6SRichard Henderson
32*121c8dd6SRichard Henderson g_free(isa_string);
33*121c8dd6SRichard Henderson return 0;
34*121c8dd6SRichard Henderson }
35*121c8dd6SRichard Henderson #define HAVE_ARCH_PROC_CPUINFO
36*121c8dd6SRichard Henderson
37*121c8dd6SRichard Henderson #endif /* RISCV_TARGET_PROC_H */
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