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Searched refs:val32 (Results 1 – 12 of 12) sorted by relevance

/qemu/hw/misc/
H A Dsifive_u_otp.c107 uint32_t val32 = (uint32_t)val64; in sifive_u_otp_write() local
111 s->pa = val32 & SIFIVE_U_OTP_PA_MASK; in sifive_u_otp_write()
114 s->paio = val32; in sifive_u_otp_write()
117 s->pas = val32; in sifive_u_otp_write()
120 s->pce = val32; in sifive_u_otp_write()
123 s->pclk = val32; in sifive_u_otp_write()
126 s->pdin = val32; in sifive_u_otp_write()
132 s->pdstb = val32; in sifive_u_otp_write()
135 s->pprog = val32; in sifive_u_otp_write()
138 s->ptc = val32; in sifive_u_otp_write()
[all …]
H A Dsifive_u_prci.c62 uint32_t val32 = (uint32_t)val64; in sifive_u_prci_write() local
66 s->hfxosccfg = val32; in sifive_u_prci_write()
71 s->corepllcfg0 = val32; in sifive_u_prci_write()
78 s->ddrpllcfg0 = val32; in sifive_u_prci_write()
85 s->ddrpllcfg1 = val32; in sifive_u_prci_write()
88 s->gemgxlpllcfg0 = val32; in sifive_u_prci_write()
95 s->gemgxlpllcfg1 = val32; in sifive_u_prci_write()
98 s->coreclksel = val32; in sifive_u_prci_write()
101 s->devicesreset = val32; in sifive_u_prci_write()
104 s->clkmuxstatus = val32; in sifive_u_prci_write()
[all …]
H A Daspeed_xdma.c66 uint32_t val32 = (uint32_t)val; in aspeed_xdma_write() local
75 xdma->regs[TO_REG(addr)] = val32 & XDMA_BMC_CMDQ_W_MASK; in aspeed_xdma_write()
78 xdma->regs[idx] = val32 & XDMA_BMC_CMDQ_W_MASK; in aspeed_xdma_write()
95 if (val32 == XDMA_BMC_CMDQ_RDP_MAGIC) { in aspeed_xdma_write()
99 xdma->regs[TO_REG(addr)] = val32 & axc->intr_ctrl_mask; in aspeed_xdma_write()
104 if (val32 & axc->intr_complete) { in aspeed_xdma_write()
109 xdma->regs[TO_REG(addr)] = val32; in aspeed_xdma_write()
H A Dxlnx-versal-pmc-iou-slcr.c873 uint32_t val32 = (uint32_t) val64; in ospi_qspi_iou_axi_mux_sel_prew() local
874 uint8_t ospi_mux_sel = FIELD_EX32(val32, OSPI_QSPI_IOU_AXI_MUX_SEL, in ospi_qspi_iou_axi_mux_sel_prew()
876 uint8_t qspi_ospi_mux_sel = FIELD_EX32(val32, OSPI_QSPI_IOU_AXI_MUX_SEL, in ospi_qspi_iou_axi_mux_sel_prew()
/qemu/hw/ssi/
H A Dibex_spi_host.c346 uint32_t val32 = val64; in ibex_spi_host_write() local
359 if (FIELD_EX32(val32, INTR_STATE, ERROR)) { in ibex_spi_host_write()
362 if (FIELD_EX32(val32, INTR_STATE, SPI_EVENT)) { in ibex_spi_host_write()
368 s->regs[addr] = val32; in ibex_spi_host_write()
371 s->regs[addr] = val32; in ibex_spi_host_write()
375 s->regs[addr] = val32; in ibex_spi_host_write()
380 s->regs[addr] = val32; in ibex_spi_host_write()
382 if (val32 & R_CONTROL_SW_RST_MASK) { in ibex_spi_host_write()
388 if (val32 & R_CONTROL_OUTPUT_EN_MASK) { in ibex_spi_host_write()
395 s->config_opts[s->regs[IBEX_SPI_HOST_CSID]] = val32; in ibex_spi_host_write()
[all …]
/qemu/hw/sd/
H A Dcadence_sdhci.c83 uint32_t val32 = (uint32_t)val; in cadence_sdhci_write() local
91 if (val32 & CADENCE_SDHCI_HRS00_SWR) { in cadence_sdhci_write()
101 if (val32 & (CADENCE_SDHCI_HRS04_WR | CADENCE_SDHCI_HRS04_RD)) { in cadence_sdhci_write()
102 val32 |= CADENCE_SDHCI_HRS04_ACK; in cadence_sdhci_write()
104 val32 &= ~CADENCE_SDHCI_HRS04_ACK; in cadence_sdhci_write()
107 s->regs[TO_REG(addr)] = val32; in cadence_sdhci_write()
110 if (val32 & CADENCE_SDHCI_HRS06_TUNE_UP) { in cadence_sdhci_write()
111 val32 &= ~CADENCE_SDHCI_HRS06_TUNE_UP; in cadence_sdhci_write()
114 s->regs[TO_REG(addr)] = val32; in cadence_sdhci_write()
117 s->regs[TO_REG(addr)] = val32; in cadence_sdhci_write()
/qemu/hw/char/
H A Dmchp_pfsoc_mmuart.c50 uint32_t val32 = (uint32_t)value; in mchp_pfsoc_mmuart_write() local
55 " v=0x%x\n", __func__, addr << 2, val32); in mchp_pfsoc_mmuart_write()
59 s->reg[addr] = val32; in mchp_pfsoc_mmuart_write()
/qemu/target/hexagon/
H A Dgenptr.c107 TCGv val32 = tcg_temp_new(); in gen_log_reg_write_pair() local
110 tcg_gen_extrl_i64_i32(val32, val); in gen_log_reg_write_pair()
111 gen_log_reg_write(ctx, rnum, val32); in gen_log_reg_write_pair()
114 tcg_gen_extrh_i64_i32(val32, val); in gen_log_reg_write_pair()
115 gen_log_reg_write(ctx, rnum + 1, val32); in gen_log_reg_write_pair()
261 TCGv val32 = tcg_temp_new(); in gen_write_ctrl_reg_pair() local
262 tcg_gen_extrl_i64_i32(val32, val); in gen_write_ctrl_reg_pair()
263 gen_write_p3_0(ctx, val32); in gen_write_ctrl_reg_pair()
264 tcg_gen_extrh_i64_i32(val32, val); in gen_write_ctrl_reg_pair()
265 tcg_gen_mov_tl(result, val32); in gen_write_ctrl_reg_pair()
/qemu/hw/intc/
H A Dopenpic_kvm.c64 uint32_t val32 = val; in kvm_openpic_write() local
69 attr.addr = (uint64_t)(unsigned long)&val32; in kvm_openpic_write()
/qemu/hw/net/
H A Drtl8139.c1302 uint32_t val32; in RTL8139TallyCounters_dma_write() local
1314 val32 = cpu_to_le32(tally_counters->RxERR); in RTL8139TallyCounters_dma_write()
1315 pci_dma_write(d, tc_addr + 24, (uint8_t *)&val32, 4); in RTL8139TallyCounters_dma_write()
1323 val32 = cpu_to_le32(tally_counters->Tx1Col); in RTL8139TallyCounters_dma_write()
1324 pci_dma_write(d, tc_addr + 32, (uint8_t *)&val32, 4); in RTL8139TallyCounters_dma_write()
1326 val32 = cpu_to_le32(tally_counters->TxMCol); in RTL8139TallyCounters_dma_write()
1327 pci_dma_write(d, tc_addr + 36, (uint8_t *)&val32, 4); in RTL8139TallyCounters_dma_write()
1335 val32 = cpu_to_le32(tally_counters->RxOkMul); in RTL8139TallyCounters_dma_write()
1336 pci_dma_write(d, tc_addr + 56, (uint8_t *)&val32, 4); in RTL8139TallyCounters_dma_write()
/qemu/target/arm/tcg/
H A Dhelper-a64.c297 uint32_t val32, sbit; in HELPER() local
316 val32 = float32_val(a); in HELPER()
317 sbit = 0x80000000ULL & val32; in HELPER()
318 exp = extract32(val32, 23, 8); in HELPER()
/qemu/target/riscv/kvm/
H A Dkvm-cpu.c265 uint32_t *val32 = kvmconfig_get_env_addr(cpu, csr_cfg); in kvm_cpu_csr_get_u32() local
266 return *val32; in kvm_cpu_csr_get_u32()
278 uint32_t *val32 = kvmconfig_get_env_addr(cpu, csr_cfg); in kvm_cpu_csr_set_u32() local
279 *val32 = val; in kvm_cpu_csr_set_u32()