346     uint32_t val32 = val64;  in ibex_spi_host_write()  local
359         if (FIELD_EX32(val32, INTR_STATE, ERROR)) {  in ibex_spi_host_write()
362         if (FIELD_EX32(val32, INTR_STATE, SPI_EVENT)) {  in ibex_spi_host_write()
368         s->regs[addr] = val32;  in ibex_spi_host_write()
371         s->regs[addr] = val32;  in ibex_spi_host_write()
375         s->regs[addr] = val32;  in ibex_spi_host_write()
380         s->regs[addr] = val32;  in ibex_spi_host_write()
382         if (val32 & R_CONTROL_SW_RST_MASK)  {  in ibex_spi_host_write()
388         if (val32 & R_CONTROL_OUTPUT_EN_MASK)  {  in ibex_spi_host_write()
395         s->config_opts[s->regs[IBEX_SPI_HOST_CSID]] = val32;  in ibex_spi_host_write()
401         if (val32 >= s->num_cs) {  in ibex_spi_host_write()
408         s->regs[addr] = val32;  in ibex_spi_host_write()
411         s->regs[addr] = val32;  in ibex_spi_host_write()
430         if (FIELD_EX32(val32, COMMAND, DIRECTION) != BIDIRECTIONAL_TRANSFER) {  in ibex_spi_host_write()
435         if (val32 & R_COMMAND_CSAAT_MASK)  {  in ibex_spi_host_write()
439         if (val32 & R_COMMAND_SPEED_MASK)  {  in ibex_spi_host_write()
481             fifo8_push(&s->tx_fifo, (val32 & shift_mask) >> (i * 8));  in ibex_spi_host_write()
497         s->regs[addr] = val32;  in ibex_spi_host_write()
499         if (val32 & R_ERROR_ENABLE_CMDINVAL_MASK)  {  in ibex_spi_host_write()
512         if (FIELD_EX32(val32, ERROR_STATUS, CMDBUSY)) {  in ibex_spi_host_write()
515         if (FIELD_EX32(val32, ERROR_STATUS, OVERFLOW)) {  in ibex_spi_host_write()
518         if (FIELD_EX32(val32, ERROR_STATUS, UNDERFLOW)) {  in ibex_spi_host_write()
521         if (FIELD_EX32(val32, ERROR_STATUS, CMDINVAL)) {  in ibex_spi_host_write()
524         if (FIELD_EX32(val32, ERROR_STATUS, CSIDINVAL)) {  in ibex_spi_host_write()
527         if (FIELD_EX32(val32, ERROR_STATUS, ACCESSINVAL)) {  in ibex_spi_host_write()
534         s->regs[addr] = val32;  in ibex_spi_host_write()
536         if (val32 & R_EVENT_ENABLE_RXWM_MASK)  {  in ibex_spi_host_write()
540         if (val32 & R_EVENT_ENABLE_TXWM_MASK)  {  in ibex_spi_host_write()
545         if (val32 & R_EVENT_ENABLE_IDLE_MASK)  {  in ibex_spi_host_write()