Searched refs:tx_count (Results 1 – 6 of 6) sorted by relevance
134 s->r[R_SR] |= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL in uart_update_status()136 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0; in uart_update_status()137 s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0; in uart_update_status()163 s->tx_count = 0; in uart_tx_reset()255 ret = MIN(ret, CADENCE_UART_TX_FIFO_SIZE - s->tx_count); in uart_can_receive()309 s->tx_count = 0; in cadence_uart_xmit()313 if (!s->tx_count) { in cadence_uart_xmit()317 ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_count); in cadence_uart_xmit()320 s->tx_count -= ret; in cadence_uart_xmit()321 memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count); in cadence_uart_xmit()[all …]
36 uint32_t tx_count; member52 s->tx_count = 0; in mipsnet_reset()135 ret = s->tx_count; in mipsnet_ioport_read()172 s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0; in mipsnet_ioport_write()195 || (s->tx_written == s->tx_count)) { in mipsnet_ioport_write()200 s->tx_count = s->tx_written = 0; in mipsnet_ioport_write()225 VMSTATE_UINT32(tx_count, MIPSnetState),
48 uint32_t tx_count; member
550 g_assert(le16_to_cpu(pio->tx_count) == 12 || in ahci_port_check_pio_sanity()551 le16_to_cpu(pio->tx_count) == 16); in ahci_port_check_pio_sanity()558 g_assert_cmphex(le16_to_cpu(pio->tx_count), ==, pio_len); in ahci_port_check_pio_sanity()
400 uint16_t tx_count; member
559 uint32_t tx_count; member