134     s->r[R_SR] |= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL  in uart_update_status()
136     s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0;  in uart_update_status()
137     s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0;  in uart_update_status()
163     s->tx_count = 0;  in uart_tx_reset()
255         ret = MIN(ret, CADENCE_UART_TX_FIFO_SIZE - s->tx_count);  in uart_can_receive()
309         s->tx_count = 0;  in cadence_uart_xmit()
313     if (!s->tx_count) {  in cadence_uart_xmit()
317     ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_count);  in cadence_uart_xmit()
320         s->tx_count -= ret;  in cadence_uart_xmit()
321         memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count);  in cadence_uart_xmit()
324     if (s->tx_count) {  in cadence_uart_xmit()
328             s->tx_count = 0;  in cadence_uart_xmit()
344     if (size > CADENCE_UART_TX_FIFO_SIZE - s->tx_count) {  in uart_write_tx_fifo()
345         size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count;  in uart_write_tx_fifo()
355     memcpy(s->tx_fifo + s->tx_count, buf, size);  in uart_write_tx_fifo()
356     s->tx_count += size;  in uart_write_tx_fifo()
612         VMSTATE_UINT32(tx_count, CadenceUARTState),