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Searched refs:tmp0 (Results 1 – 9 of 9) sorted by relevance

/qemu/tests/tcg/aarch64/system/
H A Dmte.S13 #define tmp0 x2 /* Scratch register. */ macro
35 mrs tmp0, mair_el1
36 orr tmp0, tmp0, (0xF0 << 8)
37 msr mair_el1, tmp0
81 mov tmp0, 0xA5
82 msr gcr_el1, tmp0
/qemu/target/rx/
H A Dop_helper.c201 uint8_t tmp0, tmp1; in helper_scmpu() local
206 tmp0 = cpu_ldub_data_ra(env, env->regs[1]++, GETPC()); in helper_scmpu()
209 if (tmp0 != tmp1 || tmp0 == '\0') { in helper_scmpu()
213 env->psw_z = tmp0 - tmp1; in helper_scmpu()
214 env->psw_c = (tmp0 >= tmp1); in helper_scmpu()
327 int64_t tmp0, tmp1; in helper_rmpa() local
339 tmp0 = cpu_ldfn[sz](env, env->regs[1], GETPC()); in helper_rmpa()
341 tmp0 *= tmp1; in helper_rmpa()
343 result_l += tmp0; in helper_rmpa()
345 if (tmp0 < 0) { in helper_rmpa()
H A Dtranslate.c1703 TCGv_i64 tmp0, tmp1; in rx_mul64hi() local
1704 tmp0 = tcg_temp_new_i64(); in rx_mul64hi()
1706 tcg_gen_ext_i32_i64(tmp0, cpu_regs[rs]); in rx_mul64hi()
1707 tcg_gen_sari_i64(tmp0, tmp0, 16); in rx_mul64hi()
1710 tcg_gen_mul_i64(ret, tmp0, tmp1); in rx_mul64hi()
1716 TCGv_i64 tmp0, tmp1; in rx_mul64lo() local
1717 tmp0 = tcg_temp_new_i64(); in rx_mul64lo()
1719 tcg_gen_ext_i32_i64(tmp0, cpu_regs[rs]); in rx_mul64lo()
1720 tcg_gen_ext16s_i64(tmp0, tmp0); in rx_mul64lo()
1723 tcg_gen_mul_i64(ret, tmp0, tmp1); in rx_mul64lo()
/qemu/target/mips/tcg/
H A Dop_helper.c55 uint64_t tmp0 = ((uint64_t)rs) << 32 | ((uint64_t)rs & 0xffffffff); in helper_rotx() local
56 uint64_t tmp1 = tmp0; in helper_rotx()
69 if (tmp0 & (1LL << (i + 16))) { in helper_rotx()
/qemu/target/loongarch/tcg/
H A Dtlb_helper.c614 target_ulong phys, tmp0, ptindex, ptoffset0, ptoffset1, ps, badv; in helper_ldpte() local
650 tmp0 = base; in helper_ldpte()
652 tmp0 += MAKE_64BIT_MASK(ps, 1); in helper_ldpte()
662 tmp0 = ldq_phys(cs->as, phys) & TARGET_PHYS_MASK; in helper_ldpte()
667 env->CSR_TLBRELO1 = tmp0; in helper_ldpte()
669 env->CSR_TLBRELO0 = tmp0; in helper_ldpte()
/qemu/hw/s390x/
H A Dcss.c751 CCW0 tmp0; in copy_ccw_from_guest() local
762 cpu_physical_memory_read(addr, &tmp0, sizeof(tmp0)); in copy_ccw_from_guest()
763 if ((tmp0.cmd_code & 0x0f) == CCW_CMD_TIC) { in copy_ccw_from_guest()
768 ret.cmd_code = tmp0.cmd_code; in copy_ccw_from_guest()
769 ret.flags = tmp0.flags; in copy_ccw_from_guest()
770 ret.count = be16_to_cpu(tmp0.count); in copy_ccw_from_guest()
772 ret.cda = be16_to_cpu(tmp0.cda1) | (tmp0.cda0 << 16); in copy_ccw_from_guest()
/qemu/target/ppc/translate/
H A Dvmx-impl.c.inc2763 TCGv_i64 tmp0, tmp1, prod1h, prod1l, prod0h, prod0l, zero;
2768 tmp0 = tcg_temp_new_i64();
2777 get_avr64(tmp0, a->vra, false);
2779 tcg_gen_mulu2_i64(prod1l, prod1h, tmp0, tmp1);
2782 get_avr64(tmp0, a->vra, true);
2784 tcg_gen_mulu2_i64(prod0l, prod0h, tmp0, tmp1);
2788 tcg_gen_add2_i64(tmp1, tmp0, tmp1, zero, prod1l, zero);
2789 tcg_gen_add2_i64(tmp1, tmp0, tmp1, tmp0, prod0l, zero);
2796 tcg_gen_add2_i64(tmp1, tmp0, tmp0, zero, tmp1, zero);
2797 tcg_gen_add2_i64(tmp1, tmp0, tmp1, tmp0, prod1h, zero);
[all …]
/qemu/target/hexagon/idef-parser/
H A DREADME.rst641 add_i32 tmp0,r2,r2
642 mov_i32 loc2,tmp0
646 Here we have finally located our bug ``add_i32 tmp0,r2,r2``.
/qemu/tcg/aarch64/
H A Dtcg-target.c.inc1671 /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {tmp0,tmp1}. */