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Searched refs:timers (Results 1 – 25 of 35) sorted by relevance

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/qemu/hw/misc/
H A Dmos6522.c256 MOS6522Timer *ti = &s->timers[0]; in mos6522_timer1()
266 MOS6522Timer *ti = &s->timers[1]; in mos6522_timer2()
303 if (now >= s->timers[0].next_irq_time) { in mos6522_read()
304 mos6522_timer1_update(s, &s->timers[0], now); in mos6522_read()
307 if (now >= s->timers[1].next_irq_time) { in mos6522_read()
308 mos6522_timer2_update(s, &s->timers[1], now); in mos6522_read()
340 val = get_counter(s, &s->timers[0]) & 0xff; in mos6522_read()
345 val = get_counter(s, &s->timers[0]) >> 8; in mos6522_read()
349 val = s->timers[0].latch & 0xff; in mos6522_read()
353 val = (s->timers[0].latch >> 8) & 0xff; in mos6522_read()
[all …]
/qemu/hw/timer/
H A Dgrlib_gptimer.c87 GPTimer *timers; member
155 ptimer_transaction_begin(unit->timers[i].ptimer); in grlib_gptimer_set_scaler()
156 ptimer_set_freq(unit->timers[i].ptimer, value); in grlib_gptimer_set_scaler()
157 ptimer_transaction_commit(unit->timers[i].ptimer); in grlib_gptimer_set_scaler()
217 value = ptimer_get_count(unit->timers[id].ptimer); in grlib_gptimer_read()
222 value = unit->timers[id].reload; in grlib_gptimer_read()
227 trace_grlib_gptimer_readl(id, addr, unit->timers[id].config); in grlib_gptimer_read()
228 return unit->timers[id].config; in grlib_gptimer_read()
282 grlib_gptimer_tx_begin(&unit->timers[id]); in grlib_gptimer_write()
283 unit->timers[id].counter = value; in grlib_gptimer_write()
[all …]
H A Dxilinx_timer.c82 struct xlx_timer *timers; member
102 csr = t->timers[i].regs[R_TCSR]; in timer_update_irq()
120 xt = &t->timers[timer]; in timer_read()
171 xt = &t->timers[timer]; in timer_write()
239 t->timers = g_malloc0(sizeof t->timers[0] * num_timers(t)); in xilinx_timer_realize()
241 struct xlx_timer *xt = &t->timers[i]; in xilinx_timer_realize()
H A Daspeed_timer.c64 const AspeedTimer (*timers)[] = (void *)t - (t->id * sizeof(*t)); in timer_to_ctrl() local
65 return container_of(timers, AspeedTimerCtrlState, timers); in timer_to_ctrl()
252 value = aspeed_timer_get_value(&s->timers[(offset >> 4)], reg); in aspeed_timer_read_common()
255 value = aspeed_timer_get_value(&s->timers[(offset >> 4) - 1], reg); in aspeed_timer_read_common()
273 t = &s->timers[timer]; in aspeed_timer_set_value()
409 t = &s->timers[i]; in aspeed_timer_set_ctrl()
642 t = &s->timers[index]; in aspeed_2700_timer_set_ctrl()
695 t = &s->timers[index]; in aspeed_2700_timer_clear_ctrl()
753 value = aspeed_timer_get_value(&s->timers[timer_index], in aspeed_2700_timer_read()
814 AspeedTimer *t = &s->timers[id]; in aspeed_init_one_timer()
[all …]
H A Dmss-timer.c105 st = &t->timers[timer]; in timer_read()
154 st = &t->timers[timer]; in timer_write()
233 struct Msf2Timer *st = &t->timers[i]; in mss_timer_init()
253 struct Msf2Timer *st = &t->timers[i]; in mss_timer_finalize()
276 VMSTATE_STRUCT_ARRAY(timers, MSSTimerState, NUM_TIMERS, 0,
/qemu/scripts/
H A Dqemu-gdb.py26 from qemugdb import aio, mtree, coroutine, tcg, timers
39 timers.TimersCommand()
/qemu/hw/intc/
H A Dopenpic.c770 if ((opp->timers[idx].tbcr & TBCR_CI) != (val & TBCR_CI)) { in openpic_tmr_write()
773 opp->timers[idx].tccr = val & ~TCCR_TOG; in openpic_tmr_write()
775 openpic_tmr_set_tmr(&opp->timers[idx], in openpic_tmr_write()
779 opp->timers[idx].tbcr = val; in openpic_tmr_write()
809 retval = openpic_tmr_get_timer(&opp->timers[idx]); in openpic_tmr_read()
812 retval = opp->timers[idx].tbcr; in openpic_tmr_read()
1307 opp->timers[i].tccr = 0; in openpic_reset()
1308 opp->timers[i].tbcr = TBCR_CI; in openpic_reset()
1309 if (opp->timers[i].qemu_timer_active) { in openpic_reset()
1310 timer_del(opp->timers[i].qemu_timer); /* Inhibit timer */ in openpic_reset()
[all …]
H A Driscv_aclint.c109 timer_mod(mtimer->timers[hartid], next); in riscv_aclint_mtimer_write_timecmp()
291 s->timers = g_new0(QEMUTimer *, s->num_harts); in riscv_aclint_mtimer_realize()
391 s->timers[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL, in riscv_aclint_mtimer_create()
/qemu/rust/hw/timer/hpet/src/
H A Ddevice.rs40 /// Maximum timers in each timer block.
240 &state.timers[self.index as usize], in init()
309 // bits for timers 0 and 1 (APIC or FSB) will have no impact. in get_int_route()
322 // routing bits for each of the timers are used. in get_int_route()
557 /// the timers' interrupt can be routed, and is encoded in the
564 timers: [BqlRefCell<HPETTimer>; HPET_MAX_TIMERS], field
611 for (index, timer) in self.timers.iter().enumerate() { in handle_legacy_irq()
634 for timer in self.timers.iter().take(self.num_timers) { in set_cfg_reg()
646 for timer in self.timers.iter().take(self.num_timers) { in set_cfg_reg()
669 for (index, timer) in self.timers
[all...]
/qemu/docs/devel/
H A Dreplay.rst66 in sequence (e.g. expiring timers and checkpoints in the main thread
87 from timers, asynchronous input-output, and bottom halves.
89 Invocations of timers are coupled with clock reads and changing the state
98 QEMU in replay mode will try to invoke timers processing in random moment
99 of time. That's why we do not process a group of timers until the checkpoint
130 at the specified moments of time. There are several kinds of timers:
134 clock and timers does not affect deterministic replay at all.
135 * Virtual clock. These timers run only during the emulation. In icount
147 All virtual devices should use virtual clock for timers that change the guest
148 state. Virtual clock is deterministic, therefore such timers are deterministic
[all …]
/qemu/tests/unit/
H A Dtest-throttle.c172 g_assert(tt->timers[THROTTLE_READ]); in test_init()
173 g_assert(tt->timers[THROTTLE_WRITE]); in test_init()
204 g_assert(tt->timers[THROTTLE_READ]); in test_init_readonly()
205 g_assert(!tt->timers[THROTTLE_WRITE]); in test_init_readonly()
236 g_assert(!tt->timers[THROTTLE_READ]); in test_init_writeonly()
237 g_assert(tt->timers[THROTTLE_WRITE]); in test_init_writeonly()
259 g_assert(!tt->timers[i]); in test_destroy()
/qemu/include/hw/timer/
H A Dmss-timer.h60 struct Msf2Timer timers[NUM_TIMERS]; member
H A Daspeed_timer.h66 AspeedTimer timers[ASPEED_TIMER_NR_TIMERS]; member
/qemu/block/
H A Dthrottle-groups.c346 timer_mod(tt->timers[direction], now); in schedule_next_request()
441 assert(!timer_pending(tgm->throttle_timers.timers[direction])); in throttle_group_restart_queue()
455 QEMUTimer *t = tgm->throttle_timers.timers[dir]; in throttle_group_restart_tgm()
604 assert(!timer_pending(tgm->throttle_timers.timers[dir])); in throttle_group_unregister_tgm()
647 if (timer_pending(tt->timers[dir])) { in throttle_group_detach_aio_context()
/qemu/util/
H A Dthrottle.c207 tt->timers[dir] = in throttle_timers_attach_aio_context()
269 throttle_timer_destroy(&tt->timers[dir]); in throttle_timers_detach_aio_context()
285 if (tt->timers[dir]) { in throttle_timers_are_initialized()
442 timer = tt->timers[direction]; in throttle_schedule_timer()
/qemu/docs/system/arm/
H A Dkzm.rst15 - EPIT timers
H A Dimx25-pdk.rst13 - EPIT timers
H A Dsabrelite.rst18 * 2 EPIC timers
20 * 2 Watchdog timers
/qemu/include/hw/intc/
H A Driscv_aclint.h36 QEMUTimer **timers; member
/qemu/system/
H A Dmeson.build14 'cpu-timers.c',
/qemu/include/qemu/
H A Dthrottle.h109 QEMUTimer *timers[THROTTLE_MAX]; /* timers used to do the throttling */ member
/qemu/include/hw/misc/
H A Dmos6522.h146 MOS6522Timer timers[2]; member
/qemu/include/hw/ppc/
H A Dopenpic.h165 OpenPICTimer timers[OPENPIC_MAX_TMR]; member
/qemu/docs/system/i386/
H A Dhyperv.rst90 is needed to enable Hyper-V synthetic timers. SynIC is controlled through MSRs
97 Enables Hyper-V synthetic timers. There are four synthetic timers per virtual
99 (0x400000B0..0x400000B7) MSRs. These timers can work either in single-shot or
175 use synthetic timers in direct mode and thus ``hv-stimer-direct`` needs to be
/qemu/docs/system/
H A Dtarget-sparc.rst45 - Slave I/O: timers, interrupt controllers, Zilog serial ports,

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