770         if ((opp->timers[idx].tbcr & TBCR_CI) != (val & TBCR_CI)) {  in openpic_tmr_write()
773                 opp->timers[idx].tccr = val & ~TCCR_TOG;  in openpic_tmr_write()
775             openpic_tmr_set_tmr(&opp->timers[idx],  in openpic_tmr_write()
779         opp->timers[idx].tbcr = val;  in openpic_tmr_write()
809         retval = openpic_tmr_get_timer(&opp->timers[idx]);  in openpic_tmr_read()
812         retval = opp->timers[idx].tbcr;  in openpic_tmr_read()
1307         opp->timers[i].tccr = 0;  in openpic_reset()
1308         opp->timers[i].tbcr = TBCR_CI;  in openpic_reset()
1309         if (opp->timers[i].qemu_timer_active) {  in openpic_reset()
1310             timer_del(opp->timers[i].qemu_timer);  /* Inhibit timer */  in openpic_reset()
1311             opp->timers[i].qemu_timer_active = false;  in openpic_reset()
1365         opp->timers[i].n_IRQ = opp->irq_tim0 + i;  in fsl_common_init()
1366         opp->timers[i].qemu_timer_active = false;  in fsl_common_init()
1367         opp->timers[i].qemu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,  in fsl_common_init()
1369                                                  &opp->timers[i]);  in fsl_common_init()
1370         opp->timers[i].opp = opp;  in fsl_common_init()
1483         VMSTATE_STRUCT_ARRAY(timers, OpenPICState, OPENPIC_MAX_TMR, 0,