Home
last modified time | relevance | path

Searched refs:rs2 (Results 1 – 25 of 41) sorted by relevance

12

/qemu/target/riscv/
H A Dcrypto_helper.c30 target_ulong rs1, target_ulong rs2, in aes32_operation() argument
33 uint8_t si = rs2 >> shamt; in aes32_operation()
56 target_ulong HELPER(aes32esmi)(target_ulong rs1, target_ulong rs2, in HELPER()
59 return aes32_operation(shamt, rs1, rs2, true, true); in HELPER()
62 target_ulong HELPER(aes32esi)(target_ulong rs1, target_ulong rs2, in HELPER()
65 return aes32_operation(shamt, rs1, rs2, true, false); in HELPER()
68 target_ulong HELPER(aes32dsmi)(target_ulong rs1, target_ulong rs2, in HELPER()
71 return aes32_operation(shamt, rs1, rs2, false, true); in HELPER()
74 target_ulong HELPER(aes32dsi)(target_ulong rs1, target_ulong rs2, in HELPER()
77 return aes32_operation(shamt, rs1, rs2, false, false); in HELPER()
[all …]
H A Dfpu_helper.c120 static uint64_t do_fmadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2, in do_fmadd_h() argument
124 float16 frs2 = check_nanbox_h(env, rs2); in do_fmadd_h()
130 static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2, in do_fmadd_s() argument
134 float32 frs2 = check_nanbox_s(env, rs2); in do_fmadd_s()
217 uint64_t helper_fadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) in helper_fadd_s() argument
220 float32 frs2 = check_nanbox_s(env, rs2); in helper_fadd_s()
224 uint64_t helper_fsub_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) in helper_fsub_s() argument
227 float32 frs2 = check_nanbox_s(env, rs2); in helper_fsub_s()
231 uint64_t helper_fmul_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) in helper_fmul_s() argument
234 float32 frs2 = check_nanbox_s(env, rs2); in helper_fmul_s()
[all …]
H A Dbitmanip_helper.c27 target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2) in HELPER()
32 if ((rs2 >> i) & 1) { in HELPER()
40 target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2) in HELPER()
45 if ((rs2 >> i) & 1) { in HELPER()
106 static inline target_ulong do_xperm(target_ulong rs1, target_ulong rs2, in do_xperm() argument
115 pos = ((rs2 >> i) & mask) << sz_log2; in do_xperm()
123 target_ulong HELPER(xperm4)(target_ulong rs1, target_ulong rs2) in HELPER()
125 return do_xperm(rs1, rs2, 2); in HELPER()
128 target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2) in HELPER()
130 return do_xperm(rs1, rs2, 3); in HELPER()
H A Dinsn16.decode56 &r rd rs1 rs2 !extern
58 &s imm rs1 rs2 !extern
60 &b imm rs2 rs1 !extern
64 &r2_s rs1 rs2 !extern
70 @cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd
75 @cs_2 ... ... ... .. ... .. &r rs2=%rs2_3 rs1=%rs1_3 rd=%rs1_3
76 @cs_q ... ... ... .. ... .. &s imm=%uimm_cl_q rs1=%rs1_3 rs2=%rs2_3
77 @cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
78 @cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
80 @cb_z ... ... ... .. ... .. &b imm=%imm_cb rs1=%rs1_3 rs2=0
[all …]
H A Dinsn32.decode21 %rs2 20:5
46 &b imm rs2 rs1
49 &r rd rs1 rs2
51 &r2_s rs1 rs2
52 &s imm rs1 rs2
55 &atomic aq rl rs2 rs1 rd
56 &rmrr vm rd rs1 rs2
57 &rmr vm rd rs2
59 &rnfvm vm rd rs1 rs2 nf
60 &k_aes shamt rs2 rs1 rd
[all …]
H A Dxthead.decode18 %rs2 20:5
26 &r rd rs1 rs2 !extern
31 &th_memidx rd rs1 rs2 imm2
36 @rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
37 @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
43 @th_memidx ..... .. ..... ..... ... ..... ....... &th_memidx %rd %rs1 %rs2 %imm2
53 # is applied to rs1 (for addsl) instead of rs2 (for sh[123]add).
H A DXVentanaCondOps.decode13 %rs2 20:5
18 &r rd rs1 rs2 !extern
21 @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
/qemu/target/riscv/insn_trans/
H A Dtrans_rvzfh.c.inc82 tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUW);
94 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
111 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
128 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
145 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
162 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
178 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
194 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
210 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
242 if (a->rs1 == a->rs2) { /* FMOV */
[all …]
H A Dtrans_rvf.c.inc79 tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, memop);
102 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
119 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
136 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
153 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
170 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
186 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
202 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
218 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
250 if (a->rs1 == a->rs2) { /* FMOV */
[all …]
H A Dtrans_rvd.c.inc90 tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, memop);
110 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3);
114 TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
128 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3);
132 TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
146 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3);
150 TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
164 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3);
168 TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
182 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2);
[all …]
H A Dtrans_rvzacas.c.inc68 * Encodings with odd numbered registers specified in rs2 and rd are
71 if ((a->rs2 | a->rd) & 1) {
77 TCGv_i64 src2 = get_gpr_pair(ctx, a->rs2);
106 * Encodings with odd numbered registers specified in rs2 and rd are
109 if ((a->rs2 | a->rd) & 1) {
117 TCGv_i64 src2l = get_gpr(ctx, a->rs2, EXT_NONE);
118 TCGv_i64 src2h = get_gpr(ctx, a->rs2 == 0 ? 0 : a->rs2 + 1, EXT_NONE);
H A Dtrans_rvvk.c.inc28 return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, \
48 return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \
174 vreg_ofs(s, a->rs2), tcg_env, \
188 vext_check_ss(s, a->rd, a->rs2, a->vm);
196 vext_check_ss(s, a->rd, a->rs2, a->vm);
226 return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s, \
267 tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
283 require_align(a->rs2, s->lmul) &&
296 return vaes_check_overlap(s, a->rd, a->rs2) &&
342 tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
[all …]
H A Dtrans_rvbf16.c.inc82 vreg_ofs(ctx, a->rs2), tcg_env,
107 vreg_ofs(ctx, a->rs2), tcg_env,
124 vext_check_dss(ctx, a->rd, a->rs1, a->rs2, a->vm) &&
126 vext_check_input_eew(ctx, a->rd, sew + 1, a->rs2, sew, a->vm)) {
137 vreg_ofs(ctx, a->rs2), tcg_env,
154 vext_check_ds(ctx, a->rd, a->rs2, a->vm) &&
155 vext_check_input_eew(ctx, a->rd, sew + 1, a->rs2, sew, a->vm)) {
163 return opfvf_trans(a->rd, a->rs1, a->rs2, data,
H A Dtrans_rvzfa.c.inc188 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
205 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
222 TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
239 TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
256 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
273 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
426 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
441 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
456 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
471 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
[all …]
H A Dtrans_xthead.c.inc87 * If !zext_offs, then the address is rs1 + (rs2 << imm2).
88 * If zext_offs, then the address is rs1 + (zext(rs2[31:0]) << imm2).
90 static TCGv get_th_address_indexed(DisasContext *ctx, int rs1, int rs2,
93 TCGv src2 = get_gpr(ctx, rs2, EXT_NONE);
111 * th.addsl shifts rs2.
315 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
325 /* th.mveqz: "if (rs2 == 0) rd = rs1;" */
332 /* th.mvnez: "if (rs2 != 0) rd = rs1;" */
343 * If !zext_offs, then address is rs1 + (rs2 << imm2).
344 * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2).
[all …]
H A Dtrans_rvv.c.inc237 TCGv s2 = get_gpr(s, a->rs2, EXT_ZERO);
908 uint32_t rs2, uint32_t vm, uint32_t nf,
914 TCGv stride = get_gpr(s, rs2, EXT_NONE);
1099 static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
1137 gen_ldst_stride_main_loop(s, dest, rs1, rs2, vm, nf, ld_fn, st_fn, is_load);
1162 return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, s, true);
1186 return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, s, false);
1273 return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
1280 vext_check_ld_index(s, a->rd, a->rs2, a->nf, a->vm, eew) &&
1281 vext_check_input_eew(s, -1, 0, a->rs2, eew, a->vm);
[all …]
/qemu/target/sparc/
H A Dinsns.decode47 &r_r_r rd rs1 rs2
48 @r_r_r .. rd:5 ...... rs1:5 . ........ rs2:5 &r_r_r
49 @d_r_r .. ..... ...... rs1:5 . ........ rs2:5 \
52 &r_r_r rs1=%dfp_rs1 rs2=%dfp_rs2
54 &r_r_r rd=%dfp_rd rs2=%dfp_rs2
56 &r_r_r rd=%dfp_rd rs1=%dfp_rs1 rs2=%dfp_rs2
58 &r_r_r rd=%qfp_rd rs1=%qfp_rs1 rs2=%qfp_rs2
60 &r_r_r rd=%qfp_rd rs1=%dfp_rs1 rs2=%dfp_rs2
62 @r_r_r_swap .. rd:5 ...... rs2:5 . ........ rs1:5 &r_r_r
64 &r_r_r rd=%dfp_rd rs1=%dfp_rs2 rs2=%dfp_rs1
[all …]
H A Dvis_helper.c25 target_ulong helper_array8(target_ulong rs1, target_ulong rs2) in helper_array8() argument
34 target_ulong n = MIN(rs2 & 7, 5); in helper_array8()
391 uint32_t helper_fpack16(uint64_t gsr, uint64_t rs2) in helper_fpack16() argument
399 int16_t src = rs2 >> (byte * 16); in helper_fpack16()
412 uint64_t helper_fpack32(uint64_t gsr, uint64_t rs1, uint64_t rs2) in helper_fpack32() argument
421 int32_t src = rs2 >> (word * 32); in helper_fpack32()
434 uint32_t helper_fpackfix(uint64_t gsr, uint64_t rs2) in helper_fpackfix() argument
442 int32_t src = rs2 >> (word * 32); in helper_fpackfix()
/qemu/tests/tcg/tricore/asm/
H A Dmacros.h115 #define TEST_D_DDD(insn, num, result, rs1, rs2, rs3) \ argument
118 LI(DREG_RS2, rs2); \
124 #define TEST_D_DD_PSW(insn, num, result, psw, rs1, rs2) \ argument
127 LI(DREG_RS2, rs2); \
132 #define TEST_D_DDD_PSW(insn, num, result, psw, rs1, rs2, rs3) \ argument
135 LI(DREG_RS2, rs2); \
141 #define TEST_D_DDI(insn, num, result, rs1, rs2, imm) \ argument
144 LI(DREG_RS2, rs2); \
149 #define TEST_D_DDI_PSW(insn, num, result, psw, rs1, rs2, imm) \ argument
152 LI(DREG_RS2, rs2); \
[all …]
H A Dtest_insert.S5 # insn num result rs1 imm1 rs2 imm2
14 # insn num result rs1 rs2 pos width
H A Dtest_dextr.S5 # insn num result rs1 rs2 imm
40 # insn num result rs1 rs2 rs3
/qemu/target/rx/
H A Dinsns.decode26 &rrr rd rs rs2
27 &rri rd imm rs2
30 &mr rs ld mi rs2
44 @b2_rds_li .... .... .... rd:4 &rri rs2=%b2_r_0 imm=%b2_li_8
45 @b2_rds_uimm4 .... .... imm:4 rd:4 &rri rs2=%b2_r_0
46 @b2_rs2_uimm4 .... .... imm:4 rs2:4 &rri rd=0
47 @b2_rds_imm5 .... ... imm:5 rd:4 &rri rs2=%b2_r_0
48 @b2_rd_rs_li .... .... rs2:4 rd:4 &rri imm=%b2_li_8
64 &rri rs2=%b3_r_0 imm=%b3_li_10
68 @b3_rd_rs_rs2 .... .... .... rd:4 rs:4 rs2:4 &rrr
[all …]
H A Ddisas.c394 prt("pushm\tr%d-r%d", a->rs, a->rs2); in trans_PUSHM()
458 prt("and\tr%d,r%d, r%d", a->rs, a->rs2, a->rd); in trans_AND_rrr()
481 prt("or\tr%d, r%d, r%d", a->rs, a->rs2, a->rd); in trans_OR_rrr()
567 if (a->imm < 0x10 && a->rs2 == a->rd) { in trans_ADD_irr()
570 prt("add\t#0x%08x, r%d, r%d", a->imm, a->rs2, a->rd); in trans_ADD_irr()
586 prt("add\tr%d, r%d, r%d", a->rs, a->rs2, a->rd); in trans_ADD_rrr()
595 prt_ir(ctx, "cmp", a->imm, a->rs2); in trans_CMP_ir()
625 prt("sub\tr%d, r%d, r%d", a->rs, a->rs2, a->rd); in trans_SUB_rrr()
704 prt("mul\tr%d,r%d,r%d", a->rs, a->rs2, a->rd); in trans_MUL_rrr()
773 if (a->rs2 != a->rd) { in trans_SHLL_irr()
[all …]
H A Dtranslate.c682 if (a->rs == 0 || a->rs >= a->rs2) { in trans_PUSHM()
684 "Invalid register ranges r%d-r%d", a->rs, a->rs2); in trans_PUSHM()
686 r = a->rs2; in trans_PUSHM()
856 rx_gen_op_rrr(rx_and, a->rd, a->rs, a->rs2); in trans_AND_rrr()
886 rx_gen_op_rrr(rx_or, a->rd, a->rs, a->rs2); in trans_OR_rrr()
1020 rx_gen_op_irr(rx_add, a->rd, a->rs2, a->imm); in trans_ADD_irr()
1035 rx_gen_op_rrr(rx_add, a->rd, a->rs, a->rs2); in trans_ADD_rrr()
1074 rx_gen_op_irr(rx_cmp, 0, a->rs2, a->imm); in trans_CMP_ir()
1104 rx_gen_op_rrr(rx_sub, a->rd, a->rs2, a->rs); in trans_SUB_rrr()
1183 rx_gen_op_rrr(tcg_gen_mul_i32, a->rd, a->rs, a->rs2); in trans_MUL_rrr()
[all …]
/qemu/disas/
H A Driscv.c4565 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; in decode_inst_operands()
4570 dec->rs1 = dec->rs2 = rv_ireg_zero; in decode_inst_operands()
4575 dec->rs1 = dec->rs2 = rv_ireg_zero; in decode_inst_operands()
4581 dec->rs2 = rv_ireg_zero; in decode_inst_operands()
4587 dec->rs2 = rv_ireg_zero; in decode_inst_operands()
4593 dec->rs2 = rv_ireg_zero; in decode_inst_operands()
4599 dec->rs2 = rv_ireg_zero; in decode_inst_operands()
4605 dec->rs2 = rv_ireg_zero; in decode_inst_operands()
4611 dec->rs2 = operand_rs2(inst); in decode_inst_operands()
4617 dec->rs2 = operand_rs2(inst); in decode_inst_operands()
[all …]

12