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Searched refs:rh (Results 1 – 22 of 22) sorted by relevance

/qemu/tests/unit/
H A Dtest-mul64.c15 uint64_t rh, rl; member
43 uint64_t rl, rh; in test_u() local
44 mulu64(&rl, &rh, test_u_data[i].a, test_u_data[i].b); in test_u()
46 g_assert_cmpuint(rh, ==, test_u_data[i].rh); in test_u()
55 uint64_t rl, rh; in test_s() local
56 muls64(&rl, &rh, test_s_data[i].a, test_s_data[i].b); in test_s()
58 g_assert_cmpint(rh, ==, test_s_data[i].rh); in test_s()
/qemu/target/riscv/
H A Dm128_helper.c48 target_ulong rl, rh; in HELPER() local
53 rh = uh; in HELPER()
57 rh = int128_gethi(r); in HELPER()
60 env->retxh = rh; in HELPER()
93 target_ulong rh, rl; in HELPER() local
98 rh = uh; in HELPER()
102 rh = int128_gethi(r); in HELPER()
105 env->retxh = rh; in HELPER()
H A Dtranslate.c428 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) in gen_set_gpr128() argument
433 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); in gen_set_gpr128()
/qemu/util/
H A Dhost-utils.c44 LL rl, rm, rn, rh, a0, b0; in mul64() local
53 rh.ll = (uint64_t)a0.l.high * b0.l.high; in mul64()
58 c = c + rm.l.high + rn.l.high + rh.l.low; in mul64()
59 rh.l.low = c; in mul64()
60 rh.l.high += (uint32_t)(c >> 32); in mul64()
63 *phigh = rh.ll; in mul64()
75 uint64_t rh; in muls64() local
77 mul64(plow, &rh, a, b); in muls64()
81 rh -= a; in muls64()
84 rh -= b; in muls64()
[all …]
/qemu/target/riscv/insn_trans/
H A Dtrans_rvm.c.inc50 static void gen_mul_i128(TCGv rl, TCGv rh,
58 tcg_gen_mulu2_tl(rl, rh, rs1l, rs2l);
60 tcg_gen_add2_tl(rh, tmpx, rh, zero, tmpl, tmph);
62 tcg_gen_add2_tl(rh, tmph, rh, tmpx, tmpl, tmph);
71 static void gen_mulh_i128(TCGv rl, TCGv rh,
79 gen_mulhu_i128(rl, rh, rs1l, rs1h, rs2l, rs2h);
86 tcg_gen_sub2_tl(t0l, t0h, rl, rh, t0l, t0h);
87 tcg_gen_sub2_tl(rl, rh, t0l, t0h, t1l, t1h);
110 static void gen_mulhsu_i128(TCGv rl, TCGv rh,
117 gen_mulhu_i128(rl, rh, rs1l, rs1h, rs2l, rs2h);
[all …]
H A Dtrans_rvi.c.inc201 TCGv rh = tcg_temp_new();
211 tcg_gen_xor_tl(rh, ah, bh);
212 tcg_gen_or_tl(rl, rl, rh);
223 tcg_gen_sub2_tl(rl, rh, al, ah, bl, bh);
224 tcg_gen_xor_tl(rl, rh, ah);
227 tcg_gen_xor_tl(rl, rh, rl);
244 tcg_gen_sub2_tl(tmp, rh, ah, one, tmp, zero);
245 tcg_gen_sub2_tl(tmp, rl, tmp, rh, bh, zero);
259 static void gen_setcond_i128(TCGv rl, TCGv rh,
266 tcg_gen_movi_tl(rh, 0);
/qemu/crypto/
H A Dclmul.c98 uint64_t rl = 0, rh = 0; in clmul_64_gen() local
108 rh ^= (m >> (64 - i)) & mask; in clmul_64_gen()
110 return int128_make128(rl, rh); in clmul_64_gen()
/qemu/tcg/
H A Dtcg-op.c1084 void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, in tcg_gen_add2_i32() argument
1090 tcg_gen_op3_i32(INDEX_op_addci, rh, ah, bh); in tcg_gen_add2_i32()
1098 tcg_gen_add_i32(rh, ah, bh); in tcg_gen_add2_i32()
1099 tcg_gen_add_i32(rh, rh, t1); in tcg_gen_add2_i32()
1133 void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, in tcg_gen_sub2_i32() argument
1139 tcg_gen_op3_i32(INDEX_op_subbi, rh, ah, bh); in tcg_gen_sub2_i32()
1147 tcg_gen_sub_i32(rh, ah, bh); in tcg_gen_sub2_i32()
1148 tcg_gen_sub_i32(rh, rh, t1); in tcg_gen_sub2_i32()
1155 void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2) in tcg_gen_mulu2_i32() argument
1158 tcg_gen_op4_i32(INDEX_op_mulu2, rl, rh, arg1, arg2); in tcg_gen_mulu2_i32()
[all …]
H A Doptimize.c2133 TCGArg rl, rh; in fold_multiply2() local
2160 rh = op->args[1]; in fold_multiply2()
2166 tcg_opt_gen_movi(ctx, op2, rh, h); in fold_multiply2()
/qemu/include/tcg/
H A Dtcg-op-common.h135 void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
137 void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
141 void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
142 void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
143 void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
240 void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
242 void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
246 void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
247 void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
248 void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
/qemu/include/qemu/
H A Dhost-utils.h104 uint64_t rl, rh; in muldiv64_rounding() local
111 rh = (uint64_t)u.l.high * (uint64_t)b; in muldiv64_rounding()
112 rh += (rl >> 32); in muldiv64_rounding()
113 res.l.high = rh / c; in muldiv64_rounding()
114 res.l.low = (((rh % c) << 32) + (rl & 0xffffffff)) / c; in muldiv64_rounding()
/qemu/target/tricore/
H A Dtranslate.c181 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \ argument
187 tcg_gen_extr_i64_i32(rl, rh, ret); \
190 #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \ argument
194 tcg_gen_extr_i64_i32(rl, rh, ret); \
228 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) in gen_st_2regs_64() argument
232 tcg_gen_concat_i32_i64(temp, rl, rh); in gen_st_2regs_64()
236 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, in gen_offset_st_2regs() argument
241 gen_st_2regs_64(rh, rl, temp, ctx); in gen_offset_st_2regs()
244 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) in gen_ld_2regs_64() argument
250 tcg_gen_extr_i64_i32(rl, rh, temp); in gen_ld_2regs_64()
[all …]
H A Dop_helper.c115 uint16_t rh, rl; in reverse16() local
118 rh = (uint16_t)((low * 0x0202020202ULL & 0x010884422010ULL) % 1023); in reverse16()
120 return (rh << 8) | rl; in reverse16()
/qemu/hw/xen/
H A Dxen_pt_msi.c53 int rh, dm, dest_id, deliv_mode, trig_mode; in msi_gflags() local
55 rh = (addr >> MSI_ADDR_REDIRECTION_SHIFT) & 0x1; in msi_gflags()
61 result = dest_id | (rh << XEN_PT_GFLAGS_SHIFT_RH) in msi_gflags()
/qemu/target/hexagon/imported/
H A Dencode_pp.def92 STD_PLD_IOENC(rh, "010")
106 STD_PST_IOENC(rh, "010","ttttt")
130 STD_LD_GP(rh, "010")
139 STD_ST_GP(rh, "010","ttttt")
182 STD_PLD_RRENC(rh, "010")
194 STD_PST_RRENC(rh, "010","ttttt")
215 V4_PSTI(rh, "01")
229 STD_LD_RRENC(rh, "010")
238 STD_ST_RRENC(rh, "010","ttttt")
258 V4_STI(rh, "01")
[all …]
/qemu/tests/tcg/i386/
H A Dtest-i386.c2135 unsigned long a, d, r, rh; \
2139 rh = d;\
2140 asm volatile(#op : "=a" (r), "=d" (rh) : "0" (r), "1" (rh)); \
2141 printf("%-10s A=" FMTLX " R=" FMTLX ":" FMTLX "\n", #op, a, r, rh); \
/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_vec.c.inc357 TCGv_i64 rh, rl, ah, al, bh, bl;
363 rh = tcg_temp_new_i64();
376 func(rl, rh, al, ah, bl, bh);
378 set_vreg64(rh, a->vd, 1 + i * 2);
2127 static void tcg_gen_mulus2_i64(TCGv_i64 rl, TCGv_i64 rh,
2130 tcg_gen_mulsu2_i64(rl, rh, arg2, arg1);
2138 TCGv_i64 rh, rl, arg1, arg2;
2145 rh = tcg_temp_new_i64();
2154 func(rl, rh, arg1, arg2);
2156 set_vreg64(rh, a->vd, 2 * i + 1);
[all …]
/qemu/fpu/
H A Dsoftfloat-parts.c.inc866 uint64_t dh, dl, rh, rl, sh, sl, uh, ul; /* 128-bit computation */
1012 mul64To128(u64, r64, &rh, &rl);
1013 add128(rh, rl, rh, rl, &rh, &rl);
1016 mul128To256(a->frac_hi, a->frac_lo, rh, rl, &sh, &sl, &discard, &discard);
1017 mul128To256(sh, sl, rh, rl, &dh, &dl, &discard, &discard);
/qemu/ui/
H A Dvnc-enc-tight.c1549 int rw, rh; in send_rect_simple() local
1562 rh = MIN(max_sub_height, h - dy); in send_rect_simple()
1563 n += send_sub_rect(vs, x+dx, y+dy, rw, rh); in send_rect_simple()
/qemu/target/ppc/translate/
H A Dvmx-impl.c.inc2735 TCGv_i64 rl, rh, src1, src2;
2741 rh = tcg_temp_new_i64();
2747 get_avr64(rh, a->rc, true);
2753 tcg_gen_add2_i64(rl, rh, rl, rh, src1, src2);
2757 set_avr64(a->vrt, rh, true);
H A Dfixedpoint-impl.c.inc490 void (*helper)(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1,
/qemu/tcg/arm/
H A Dtcg-target.c.inc2868 static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh)
2872 tcg_out_vreg3(s, INSN_VORR | (1 << 12), 0, 0, rd, rh, rh);